$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Technology mapping technique for fracturable logic elements 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0745913 (2003-12-23)
발명자 / 주소
  • Ratchev,Boris
  • Hwang,Yean Yow
  • Pedersen,Bruce
출원인 / 주소
  • Altera Corporation
대리인 / 주소
    Townsend and Townsend and Crew LLP
인용정보 피인용 횟수 : 17  인용 특허 : 21

초록

A technique of minimizes circuit area on programmable logic with fracturable logic elements by using "balancing" in the technology mapping stage of the programmable logic computer-aided-design flow. A fracturable LE can be used for logic implementation in many ways, such as being used as one maximum

대표청구항

What is claimed is: 1. A method comprising: mapping a logical function into a logic block comprising a look-up table structure configurable in a first configuration having a first look-up table having X inputs, or in a second configuration having a second look-up table having Y inputs and a third l

이 특허에 인용된 특허 (21)

  1. Kitano Hiroaki,JPX, Circuit designing method and circuit designing device.
  2. Shaw Ching-Hao (Plano TX) Bosshart Patrick (Dallas TX) Matzke Douglas (Dallas TX) Kalyan Vibhu (Dallas TX) Houston Theodore W. (Richardson TX), Comprehensive logic circuit layout system.
  3. Shaw Ching-Hao (Plano TX) Bosshart Patrick (Dallas TX) Matzke Douglas (Plano TX) Kalyan Vibhu (Dallas TX) Houston Theodore (Richardson TX), Comprehensive logic circuit layout system.
  4. Sharon Sheau-Pyng Lin ; Ping-Sheng Tseng, Converification system and method.
  5. Young, Jay T.; Abid, Salim, Dedicated resource placement enhancement.
  6. Huggins Alan H. ; Schmulian David E. ; MacPherson John ; Devanney William L., Designing integrated circuit gate arrays using programmable logic device bitstreams.
  7. Lin, Sharon Sheau-Pyng; Tseng, Ping-Sheng; Chang, Chwen-Cher; Hwang, Su-Jen, Dynamic evaluation logic system and method.
  8. Tseng, Ping-Sheng, Emulation system with multiple asynchronous clocks.
  9. Narayanan Vinod (Fishkill NY) Honsinger Philip S. (Poughkeepsie NY) Liu Lok Tin (Berkeley CA), Interconnection resource assignment method for differential current switch nets.
  10. Damiano Robert ; Spillinger Ilan Yitshak ; Trevillyan Louise Helen ; Van Ginneken Lukas Paul Pieter Pepijn, Logic synthesis for logic array modules.
  11. Leaver Andrew ; Heile Francis B., Mapping heterogeneous logic elements in a programmable logic device.
  12. Anderson, Glen R., Method and apparatus for logic synthesis with elaboration.
  13. Kamal Chaudhary ; Sudip K. Nag, Method for analytical placement of cells using density surface representations.
  14. Kong, Raymond; Anderson, Jason H., Method for computing and using future costing data in signal routing.
  15. Kaviani Alireza S.,CAX, Method for implementing a programmable logic device having look-up table and product-term circuitry.
  16. Trimberger Stephen M. (San Jose CA), Method for programming an FPLD using a library-based technology mapping algorithm.
  17. Trimberger Stephen M. (San Jose CA), Method for programming an FPLD using a library-based technology mapping algorithm.
  18. Gupta, Shail Aditya; Rau, Anita B.; Sivaraman, Mukund; Conquist, Darren C.; Schreiber, Robert S.; Schlansker, Michael S., Methods and apparatus for digital circuit design generation.
  19. Agrawal, Om P.; Sharpe-Geisler, Bradley A.; Chang, Herman M.; Nguyen, Bai; Tran, Giap H., Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources.
  20. Cantone Michael R. (Westfield NJ) Woo Nam-Sung (New Providence NJ), System for synthesizing field programmable gate array implementations from high level circuit descriptions.
  21. Tseng Ping-Sheng ; Lin Sharon Sheau-Ping ; Shen Quincy Kun-Hsu, Timing-insensitive glitch-free logic system and method.

이 특허를 인용한 특허 (17)

  1. Reynolds,Bart; Bean,Keith R.; Kirkwood,Daniel P.; Barei,James F.; Ralston,Benjamin D., Comparing graphical and netlist connections of a programmable logic device.
  2. Reynolds, Bart; Bean, Keith R.; Kirkwood, Daniel P.; Barei, James F.; Ralston, Benjamin D., Constructing a model of a programmable logic device.
  3. Reynolds,Bart; Bean,Keith R.; Kirkwood,Daniel P.; Barei,James F.; Ralston,Benjamin D., Determining controlling pins for a tile module of a programmable logic device.
  4. Reynolds,Bart; Bean,Keith R.; Kirkwood,Daniel P.; Barei,James F.; Ralston,Benjamin D., Determining indices of configuration memory cell modules of a programmable logic device.
  5. Reynolds, Bart; Bean, Keith R.; Kirkwood, Daniel P.; Barei, James F.; Ralston, Benjamin D., Determining networks of a tile module of a programmable logic device.
  6. Reynolds,Bart; Bean,Keith R.; Kirkwood,Daniel P.; Barei,James F.; Ralston,Benjamin D., Determining programmable connections through a switchbox of a programmable logic device.
  7. Reynolds,Bart; Bean,Keith R.; Kirkwood,Daniel P.; Barei,James F.; Ralston,Benjamin D., Determining reachable pins of a network of a programmable logic device.
  8. Srinivasan, Sankaranarayanan; Krishnamurthy, Sridhar; Philofsky, Brian D.; Chaudhary, Kamal; Rahut, Anirban, Latch based optimization during implementation of circuit designs for programmable logic devices.
  9. Hutton,Michael; Hwang,Yean Yow; Mendel,David, Method and apparatus for facilitating an adaptive electronic design automation tool.
  10. Singhal, Love; Iyer, Mahesh; Adya, Saurabh, Method and apparatus for performing large scale consensus based clustering.
  11. Anderson, Jason H.; Wang, Qiang, Method for technology mapping considering boolean flexibility.
  12. Trimberger, Stephen M., Methods of detecting unwanted logic in designs for programmable logic devices.
  13. Hutton, Michael D.; Baeckler, Gregg William; Yuan, Jinyong; Wysocki, Chris; Djahani, Pouyan, Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers.
  14. Hutton, Michael D.; Baeckler, Gregg William; Yuan, Jinyong; Wysocki, Chris; Djahani, Pouyan, Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers.
  15. Chiu, Gordon; Singh, Deshanand; Manohararajah, Valavan; Brown, Stephen, Systems and methods for mapping arbitrary logic functions into synchronous embedded memories.
  16. Chiu,Gordon; Singh,Deshanand; Manohararajah,Valavan; Brown,Stephen, Systems and methods for mapping arbitrary logic functions into synchronous embedded memories.
  17. Pathak, Swatiben Ruturaj; Van Antwerpen, Babette; Hutton, Michael D.; Leaver, Andrew, Tracing and reporting registers removed during synthesis.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로