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Method and apparatus for pre-tabulating sub-networks

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0062014 (2002-01-31)
발명자 / 주소
  • Teig,Steven
  • Hetzel,Asmus
출원인 / 주소
  • Cadence Design Systems, Inc.
대리인 / 주소
    Stattler, Johansen &
인용정보 피인용 횟수 : 5  인용 특허 : 67

초록

Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embo

대표청구항

We claim: 1. A method of pre-tabulating sub-networks comprising: a) automatically generating a sub-network that performs a set of at least three output functions; b) based on the set of functions, generating a parameter; and c) based on the generated parameter, storing the sub-network in a storage

이 특허에 인용된 특허 (67)

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이 특허를 인용한 특허 (5)

  1. Zhuang,Nan, Method and apparatus for optimizing a logic network in a digital circuit.
  2. Teig, Steven; Hetzel, Asmus, Method and apparatus for pre-tabulating sub-networks.
  3. Teig, Steven; Hetzel, Asmus, Method and apparatus replacing sub-networks within an IC design.
  4. Liu,Yan; Zimmer,Vincent J., Optimized ordering of firmware modules in pre-boot environment.
  5. Goldberg, Evgueni; Gulati, Kanupriya, Toggle equivalence preserving logic synthesis.
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