IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
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출원번호 |
US-0691635
(2003-10-24)
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우선권정보 |
EP-03077824(2003-09-08) |
발명자
/ 주소 |
- Devos,Bruno
- Van Hille,Herbert
- Dedene,Nele
- Willem,Patrick
- Thielemans,Robbie
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출원인 / 주소 |
- BARCO, naamloze vennootschap
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
17 인용 특허 :
6 |
초록
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A pixel module for use in a large-area display has a cluster of sequentially interconnected similar pixel modules that are driven by a central controller. The module includes pixel elements that have a serial video data bus input, and command input lines that are electrically connected to inputs of
A pixel module for use in a large-area display has a cluster of sequentially interconnected similar pixel modules that are driven by a central controller. The module includes pixel elements that have a serial video data bus input, and command input lines that are electrically connected to inputs of a latch. The latch has parallel inputs and outputs which are clocked with a data dock input. Also included are a current driver device for driving the pixels, a first inverter for driving the data clock input, an address input connected to a second inverter, an EEPROM connected to the input port, and a power supply.
대표청구항
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The invention claimed is: 1. A pixel module for use in a large-area display, in particular as part of a cluster (118) of a plurality of sequentially interconnected similar pixel modules (120) and driven by a central controller (116), comprising one or more pixel elements (122), characterized in tha
The invention claimed is: 1. A pixel module for use in a large-area display, in particular as part of a cluster (118) of a plurality of sequentially interconnected similar pixel modules (120) and driven by a central controller (116), comprising one or more pixel elements (122), characterized in that it further comprises a serial video data bus input (SERIAL IN) and one or more command input lines (CMD's In) electrically connected to inputs of a latch (210) having parallel inputs and outputs and which is clocked with a data clock input (DATA CLK); a current driver device for driving said one or more pixels (122) which is electrically connected to the outputs of latch (210) and to the data clock input (DATA CLK) and which includes a serial output port (SERIAL OUT) for transmitting the serial data to the next pixel module (120) in sequence; a first inverter (214), the output of which (DATA CLK "not") can be used to drive the data clock input (DATA CLK) of the next pixel module (120) in sequence; a grayscale clock (GS CLK) input which is electrically connected to the current driver device (210) and to an output (GS CLK) to drive the gray scale input of the next pixel module (120); an address input (ODD/EVEN) which is electrically connected to a second inverter (216), the output of which (ODD/EVEN "not" ) can drive the address input (ODD/EVEN) of the next pixel module (120); an EEPROM (218) that is electrically connected to an input port ( 2C BUS) for communication with said central controller (116), which input port is also connected to an output port (2C) for connection with the next pixel module (120); and a power supply (220) input and output. 2. A pixel module according to claim 1, characterized in that the latch (210) is a multi-bit register. 3. A pixel module according to claim 1, characterized in that EEPROM (218) stores the color coordinates for each pixel ( 122) within pixel module (120). 4. A pixel module according to claim 3, characterized in that the color coordinates are stored in the form of (x,y, Y), where x and y are the coordinates of the primary emitters an Y is the brightness. 5. A pixel module according to claim 1, characterized in that EEPROM (218) contains production data and factory light output measurement data at the time of manufacture of pixel module (120). 6. A pixel module according to claim 1, characterized in that EEPROM (218) contains the identification data, the runtime, and the serial number of pixel module (120). 7. A pixel module according to claim 1, characterized in that communication between EEPROM (218) and the central controller ( 116) is accomplished using an I2C bus. 8. A pixel module according to claim 7, characterized in that said I2C bus has a standard two wire serial data bus protocol. 9. A pixel module according to claim 7, characterized in that the I2C bus has a serial clock line and a serial data line. 10. A pixel module according to claim 1, characterized in that the power supply comprises a DC/DC converter that provides a DC voltage output for powering latch (210), current driver device ( 212), first and second inverters (214-216), EEPROM ( 218), and pixels (122). 11. A pixel module according to claim 1, characterized in that each pixel (122) includes respectively a red sub-pixel ( 310), a green sub-pixel (312)and a blue sub-pixel (314), which are separately driven by the current current driver device ( 212). 12. A pixel module according to claim 11, characterized in that each sub-pixel (310-312-314) is driven by at least one current source (318) of which the input is connected to an associated shift register (316). 13. A pixel module according to claim 12, characterized in that each red sub-pixel (310) is driven by at least two current sources (318) which are each connected to an associated shift register (316). 14. A pixel module according to claim 12 or 13, characterized in that the shift registers (316) of the current driver device are sequentially interconnected, whereby the first shift register (316-01) in the sequence is connected to the latched serial data bus input (SERIAL IN) and the last shift register (316-16) in the sequence is connected to the serial output port (SERIAL OUT) of the pixel module (120). 15. A pixel module according to claim 12 or 13, characterized in that the current sources (318) are constant current devices of which the output current can be digitally corrected. 16. A pixel module according to claim 12 or 13, characterized in that the current sources (318) are formed via a custom ASIC device. 17. A pixel module according to claim 1, characterized in that the frequency of the data clock input (DATA CLK) is set between 1 to 20 MHz.
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