초록 ▼

A latch-up-free ESD protection circuit using SCR is disclosed, in which an SCR is connected between the input pad and the negative power supply; a turn-on switch and a turn-off switch are connected between the positive power supply VDD (or the input pad) and the SCR; and a transistor gating circuit

A latch-up-free ESD protection circuit using SCR is disclosed, in which an SCR is connected between the input pad and the negative power supply; a turn-on switch and a turn-off switch are connected between the positive power supply VDD (or the input pad) and the SCR; and a transistor gating circuit is connected to the turn-on switch and the turn-off switch to direct the operation of the SCR. When overvoltage stress develops over the input pad in the fast-transient mode, the turn-on switch enables the NPN transistor to switch on the SCR to form a discharging path for electrostatic discharge; and when overvoltage stress is released, the turn-off switch enables the PNP transistor to switch off the SCR, thus making it immune to any latch-up after the overvoltage stress is released, and having the advantages of fast triggering, low trigger voltage, no latch-up, and full ESD protection in the active and passive modes.

대표청구항 ▼

What is claimed is: 1. A latch-up-free ESD protection circuit using an SCR, comprising: an SCR (10) being connected across an input pad (PAD) and a negative power supply VSS; a turn-on switch (20) being connected across a positive power supply VDD and a gate of the SCR (10) to initiate the SCR (10)

What is claimed is: 1. A latch-up-free ESD protection circuit using an SCR, comprising: an SCR (10) being connected across an input pad (PAD) and a negative power supply VSS; a turn-on switch (20) being connected across a positive power supply VDD and a gate of the SCR (10) to initiate the SCR (10); a turn-off switch (30) being connected across the positive power supply VDD and the gate of the SCR (10) to switch off the SCR (10); a transistor gating circuit (40) being connected across the positive power supply VDD and the negative power supply VSS, and also being connected to the turn-on switch ( 20) and the turn-off switch (30); whereby when overvoltage stress develops over the input pad (PAD) in a forward fast-transient mode, the transistor gating circuit ( 40) initiates the turn-on switch (20) to trigger the SCR ( 10) into conduction, so that high voltage over the input pad (PAD) is rapidly decreased to a holding voltage level of the SCR (10), thus the ESD protection circuit is immune to latch-up. 2. The ESD protection circuit according to claim 1, wherein the SCR (10) is formed by an NPN transistor (12) and a PNP transistor (11), wherein an emitter of the PNP transistor ( 11) is connected to the input pad (PAD) to form an anode of the SCR (10); a base of the PNP transistor (11) is connected by a resistor RN, and the resistor RN is connected to the anode of the SCR (10); a collector of the PNP transistor (11 ) is connected to a base of the NPN transistor (12), and through a resistor RSUB is connected to the negative power supply VSS to form a cathode of the SCR (10); and the bases of the PNP transistor (11) and the base of the NPN transistor (12) act as the gate of the SCR. 3. The ESD protection circuit according to claim 2, wherein the emitter of the PNP transistor (11) is coupled to the input pad (PAD) through at least one diode (D1), and the base is connected to a junction connecting the turn-on switch (20) and the turn-off switch (30). 4. The ESD protection circuit according to claim 2, wherein the emitter of the PNP transistor (11) is coupled to the input pad (PAD) through a PMOS transistor (13), and the base is connected to a junction connecting the turn-on switch (20) and the turn-off switch (30). 5. The ESD protection circuit according to claim 1, wherein the SCR is formed by a PNP transistor (11) and an NPN transistor (12), wherein an emitter of the PNP transistor (11) forms an anode of the SCR (10); a base of the PNP transistor (11) is connected through a resistor RN, to the anode of the SCR; a collector of the PNP transistor (11) is connected to a base of the NPN transistor (12), and further through a resistor RSUB connected to the negative power supply VSS to form a cathode of the SCR (10); and the bases of the PNP transistor (11) and the NPN transistor (12) act as the gate of the SCR (10). 6. The ESD protection circuit according to claim 5, wherein the emitter of the NPN transistor (12) is coupled with a diode (D1). 7. The ESD protection circuit according to claim 5, wherein the emitter of the NPN transistor (12) is coupled with an NMOS transistor (14), and the base of the NMOS transistor (14) is connected to the transistor gating circuit (40). 8. The ESD protection circuit according to claim 2, wherein the turn-on switch (20) has a PMOS transistor (21) connected between the positive power supply VDD and the base of NPN transistor (12) and the gate of the PMOS transistor (21) is connected to the transistor gating circuit (40). 9. The ESD protection circuit according to claim 5, wherein the turn-on switch (20) has an NMOS transistor (21) connected between the positive power supply VDD and the base of the PNP transistor (11), and the gate of the NMOS transistor ( 21) is connected to the transistor gating circuit (40). 10. The ESD protection circuit according to claim 8, wherein the turn-on switch (20) comprises a voltage clamping circuit ( 22) having a Zener diode and a diode (D2) connected back-to-back, the voltage clamping circuit (22) further connects across the bases of the PNP and NPN transistors (11) (12), whereby plural discharging paths are formed even after the SCR (10) is switched off. 11. The ESD protection circuit according to claim 9, wherein the turn-on switch (20) further comprises a voltage clamping circuit (22) having a Zener diode and a diode (D2) connected back-to-back, the voltage clamping circuit (22) further connects across the bases of the PNP and NPN transistors (11) ( 12), whereby plural discharging paths are formed even after the SCR (10) is switched off. 12. The ESD protection circuit according to claim 2, wherein a source of an NMOS transistor (31) of the turn-off switch ( 30) is connected to the base of PNP transistor (11) and a gate of the NMOS transistor (31) is connected to the transistor gating circuit (40). 13. The ESD protection circuit according to claim 3, wherein a source of an NMOS transistor (31) of the turn-off switch ( 30) is connected to the base of PNP transistor (11) and a gate of the NMOS transistor (31) is connected to the transistor gating circuit (40). 14. The ESD protection circuit according to claim 4, wherein a source of an NMOS transistor (31) of the turn-off switch ( 30) is connected to the base of PNP transistor (11) and a gate of the NMOS transistor (31) is connected to the transistor gating circuit (40). 15. The ESD protection circuit according to claim 8, wherein a source of an NMOS transistor (31) of the turn-off switch ( 30) is connected to the base of PNP transistor (11) and a gate of the NMOS transistor (31) is connected to the transistor gating circuit (40). 16. The ESD protection circuit according to claim 5, wherein a drain of a PMOS transistor (31) in the turn-off switch (30 ) is connected to the base of the NPN transistor (12) of the SCR (10), and the gate of the PMOS (31) is connected to the transistor gating circuit (40). 17. The ESD protection circuit according to claim 6, wherein a drain of a PMOS transistor (31) in the turn-off switch (30 ) is connected to the base of the NPN transistor (12) of the SCR (10), and the gate of the PMOS (31) is connected to the transistor gating circuit (40). 18. The ESD protection circuit according to claim 7, wherein a drain of a PMOS transistor (31) in the turn-off switch (30 ) is connected to the base of the NPN transistor (12) of the SCR (10), and the gate of the PMOS (31) is connected to the transistor gating circuit (40). 19. The ESD protection circuit according to claim 9, wherein the drain of a PMOS transistor (31) in the turn-off switch ( 30) is connected to the base of the NPN transistor (12) of the SCR (10), and the gate of the PMOS (31) is connected to the transistor gating circuit (40). 20. The ESD protection circuit according to claim 1, wherein the transistor gating circuit (40) is formed by a capacitor and a resistor connected in series, and a junction between the capacitor and the resistor is respectively connected to the gates of the PMOS (21 ) of the turn-on switch (20) and the NMOS (31) of the turn-off switch (30), whereby through appropriate adjustment of capacitance and resistance values a time constant is tuned to control 'on/off' time of the turn-on switch (20) and the turn-off switch (30).