Integrated circuit with configuration based on parameter measurement
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-013/00
출원번호
US-0440634
(2003-05-19)
발명자
/ 주소
Wheless, Jr.,Thomas Omega
Taylor,Richard David
Keithley,Douglas Gene
출원인 / 주소
Avago Technologies General IP (Singapore) Pte. Ltd.
인용정보
피인용 횟수 :
4인용 특허 :
14
초록▼
Embodiments of the present invention provide an integrated circuit. In one embodiment, the integrated circuit comprises logic blocks, a measurement circuit and a control circuit. The measurement circuit is configured to measure operating parameters of the integrated circuit and the logic blocks and
Embodiments of the present invention provide an integrated circuit. In one embodiment, the integrated circuit comprises logic blocks, a measurement circuit and a control circuit. The measurement circuit is configured to measure operating parameters of the integrated circuit and the logic blocks and provide operating parameter data. The control circuit is configured to receive the operating parameter data, evaluate the operating parameter data to obtain configuration data and configure the integrated circuit with the configuration data.
대표청구항▼
What is claimed is: 1. An integrated circuit, comprising: logic blocks; a measurement circuit configured to measure operating parameters of the integrated circuit and the logic blocks, and provide at least one data transfer rate parameter; and a control circuit configured to receive the at least
What is claimed is: 1. An integrated circuit, comprising: logic blocks; a measurement circuit configured to measure operating parameters of the integrated circuit and the logic blocks, and provide at least one data transfer rate parameter; and a control circuit configured to receive the at least one data transfer rate parameter, evaluate the at least one data transfer rate parameter to obtain configuration data and configure the integrated circuit with the configuration data. 2. The integrated circuit of claim 1, comprising a configuration circuit configured by the control circuit with the configuration data. 3. The integrated circuit of claim 2, wherein the configuration circuit comprises an interrupt controller. 4. The integrated circuit of claim 2, wherein the configuration circuit comprises a DMA controller and DMA configuration logic. 5. The integrated circuit of claim 2, wherein the configuration circuit comprises a backplane controller and backplane configuration logic. 6. The integrated circuit of claim 1, wherein the control circuit is configured to program the integrated circuit with configuration data for an arbitration scheme. 7. The integrated circuit of claim 1, wherein and the control circuit is configured to adjust data transfer timing in the integrated circuit based at least in part on the measured data transfer rate parameter. 8. The integrated circuit of claim 7, wherein the data transfer rate parameter is chosen from a list comprising interrupt latency, DMA request latency, bandwidth and bus hold off time. 9. The integrated circuit of claim 1, wherein the measurement circuit is configured to measure a bandwidth operating parameter on a FIFO memory and the control circuit is configured to adjust at least one chosen from a list comprising a FIFO memory priority level, a FIFO threshold and FIFO memory size. 10. The integrated circuit of claim 1, comprising a DMA controller, wherein the measurement circuit is configured to measure interrupt latency of an interrupt from the DMA controller to the control circuit and the control circuit is configured to adjust the timing of the interrupt from the DMA controller. 11. The integrated circuit of claim 1, wherein the measurement circuit is configured to measure continuous addresses accessed in a memory and the control circuit is configured to adjust a burst length. 12. The integrated circuit of claim 1, wherein the measurement circuit is configured to measure a bandwidth of one of the logic blocks and the control circuit is configured to adjust a burst length of the logic block. 13. The integrated circuit of claim 1, wherein the measurement circuit is configured to measure a bandwidth operating parameter and the control circuit is configured to adjust clock speed based at least partly on the measured bandwidth operating parameter. 14. An integrated circuit, comprising: a measurement device configured to measure an internal operating parameter of the integrated circuit and provide at least one data transfer rate parameter; a control circuit configured to receive the at least one data transfer rate parameter, evaluate the at least one data transfer rate parameter to obtain configuration data and provide the configuration data; and a configuration circuit configured to receive the configuration data to configure the integrated circuit. 15. The integrated circuit of claim 14, wherein the configuration circuit is chosen from a list comprising an interrupt controller, a DMA controller and DMA configuration logic, and a backplane controller and backplane configuration logic. 16. The integrated circuit of claim 14, wherein the control circuit is configured to program the configuration circuit with priority level configuration data. 17. The integrated circuit of claim 14, wherein the measurement circuit is configured to measure a data transfer rate parameter and the control circuit is configured to provide priority level configuration data to the configuration circuit. 18. A method of configuring an integrated circuit, comprising: measuring an internal operating parameter of the integrated circuit to obtain at least one data transfer rate parameter; providing the at least one data transfer rate parameter to a control circuit; receiving the at least one data transfer rate parameter at the control circuit; evaluating the at least one data transfer rate parameter in the control circuit to obtain configuration data; and configuring a circuit with the configuration data. 19. The method of claim 18, wherein configuring the circuit comprises programming the circuit with priority level configuration data. 20. The method of claim 18, wherein configuring the circuit comprises programming the circuit with priority level configuration data.
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이 특허에 인용된 특허 (14)
Walsh Robert J. (Ashland MA), Adaptive mechanism for efficient interrupt processing.
Song Seungyoon Peter ; Mohamed Moataz A. ; Park Heonchul ; Nguyen Le T. ; Van Aken Jerry R. ; Forin Alessandro ; Raffman Andrew R., Efficient context saving and restoring in a multi-tasking computing system environment.
Park, Hee-Jun; Luo, Haobin; Hwang, Inho; Tu, Alex K., Dynamic adjustment of an interrupt latency threshold and a resource supporting a processor in a portable computing device.
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