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Method for inspecting substrate, substrate inspecting system and electron beam apparatus 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01J-037/06
출원번호 US-0985331 (2001-11-02)
우선권정보 JP-2000-351420(2000-11-17); JP-2000-364076(2000-11-30); JP-2000-384036(2000-12-18); JP-2000-394138(2000-12-26); JP-2001-003654(2001-01-11); JP-2001-008998(2001-01-17); JP-2001-023422(2001-01-31); JP-2001-026468()
발명자 / 주소
  • Nakasuji,Mamoru
  • Noji,Nobuharu
  • Satake,Tohru
  • Kimba,Toshifumi
  • Hatakeyama,Masahiro
  • Watanabe,Kenji
  • Sobukawa,Hirosi
  • Karimata,Tsutomu
  • Yoshikawa,Shoji
  • Oowada,Shin
  • Saito,Mutsumi
  • Hamashima,Muneki
출원인 / 주소
  • Ebara Corporation
대리인 / 주소
    Westerman, Hattori, Daniels &
인용정보 피인용 횟수 : 87  인용 특허 : 21

초록

The present invention relates to a substrate inspection apparatus for inspecting a pattern formed on a substrate by irradiating a charged particle beam onto the substrate. The substrate inspection apparatus comprises: an electron beam apparatus including a charged particle beam source for emitting a

대표청구항

What is claimed is: 1. A substrate inspection method comprising: emitting a primary charged particle beam from a charged particle beam source, wherein said charged particle beam source is actuated in a space charge limited region, wherein a shot noise reduction factor is smaller than 1 and said cha

이 특허에 인용된 특허 (21)

  1. Komatsu Fumio (Fuchu JPX) Miyoshi Motosuke (Minato JPX), Apparatus and method of aligning electron beam of scanning electron microscope.
  2. Nakasuji Mamoru,JPX, Apparatus and methods for inspecting wafers and masks using multiple charged-particle beams.
  3. Nakasuji Mamoru,JPX ; Okino Teruaki,JPX ; Hirayanagi Noriyuki,JPX, Apparatus for detecting or collecting secondary electrons, charged-particle beam exposure apparatus comprising same, an.
  4. Okubo, Yukiharu, Charged particle beam control element, method of fabricating charged particle beam control element, and charged beam apparatus.
  5. Petric Paul F. (Swampscott MA), Charged particle beam lithography machine incorporating localized vacuum envelope.
  6. van der Mast Karel D. (Pijnacker NLX), Charged-particle beam apparatus.
  7. Nakasuji Mamoru,JPX ; Kawata Shintaro,JPX, Charged-particle-beam (CPB) lithography apparatus, evaluation method, and CPB source.
  8. Kohama, Yoshiaki, Electron beam apparatus, and inspection instrument and inspection process thereof.
  9. Yui, Yoshikiyo, Electron gun and electron beam drawing apparatus using the same.
  10. Nakasuji Mamoru,JPX, Electron gun and electron-beam transfer apparatus comprising same.
  11. Gallarda, Harry S.; Lo, Chiwoei Wayne; Rhoads, Adam; Talbot, Christopher G., Feature-based defect detection.
  12. Sogard Michael R., Fluid bearing operable in a vacuum region.
  13. Pollock John D. (Rowley MA), Linear gas bearing with integral vacuum seal for use in serial process ion implantation equipment.
  14. Nakasuji Mamoru,JPX, Manufacturing method for electrostatic deflector.
  15. Miyoshi Motosuke (Tokyo JPX) Okumura Katsuya (Yokohama JPX), Method of testing semiconductor elements.
  16. Hamashima Muneki,JPX ; Takekoshi Hidekazu,JPX, Object observing apparatus and method for adjusting the same.
  17. Inokuchi Masayuki,JPX, Part-inspecting system.
  18. Honjo Ichiro (Kawasaki JPX) Sugishima Kenji (Kawasaki JPX) Yamabe Masaki (Kawasaki JPX), Pattern inspection apparatus and electron beam apparatus.
  19. Kawamura Yoshio (Kokubunji JPX) Moriyama Shigeo (Tama JPX) Yamamoto Tatuharu (Higashi-Murayama JPX) Uchida Fumihiko (Hachioji JPX), Processing method and equipment for processing a semiconductor device having holder/carrier with flattened surface.
  20. Yamazaki Yuichiro,JPX ; Miyoshi Motosuke,JPX, Substrate inspecting apparatus, substrate inspecting system having the same apparatus and substrate inspecting method.
  21. Kato Shigekazu (Kudamatsu JPX) Tamura Naoyuki (Kudamatsu JPX) Nishihata Kouji (Tokuyama JPX) Tsubone Tsunehiko (Hikari JPX) Itou Atsushi (Kudamatsu JPX) Nakata Kenji (Hikari JPX) Ogawa Yoshifumi (Hik, Vacuum processing system.

이 특허를 인용한 특허 (87)

  1. Son,Jang Heon; Cha,Sang Hun, Cassette and method for fabricating liquid crystal display device using the same.
  2. Enyama, Momoyo; Ohta, Hiroya, Charged particle beam apparatus and specimen inspection method.
  3. Hiroi, Takashi; Gunji, Yasuhiro; Miyai, Hiroshi; Nojiri, Masaaki, Charged particle beam device for scanning a sample using a charged particle beam to inspect the sample.
  4. Nara, Yasuhiko; Nojiri, Masaaki; Hayakawa, Kouichi; Hiroi, Takashi, Circuit-pattern inspection apparatus.
  5. Adler, David L., Confocal secondary electron imaging.
  6. Honda, Toshifumi, Defect review method and device for semiconductor device.
  7. Nakasuji,Mamoru; Satake,Tohru; Noji,Nobuharu; Sobukawa,Hirosi; Karimata,Tsutomu; Yoshikawa,Shoji; Kimba,Toshifumi; Oowada,Shin; Saito,Mutsumi; Hamashima,Muneki; Kohama,Yoshiaki; Okubo,Yukiharu, Electron beam apparatus and device production method using the electron beam apparatus.
  8. Nakasuji, Mamoru; Noji, Nabuharu; Satake, Tohru; Hatakeyama, Masahiro; Watanabe, Kenji; Kato, Takao; Sobukawa, Hirosi; Karimata, Tsutomu; Yoshikawa, Shoji; Kimba, Toshifumi; Oowada, Shin; Saito, Mutsumi; Hamashima, Muneki, Electron beam apparatus and method of manufacturing semiconductor device using the apparatus.
  9. Ichimura, Takashi; Ogashiwa, Takeshi; Agemura, Toshihide; Aoki, Kenji, Electron beam device and its control method.
  10. Imoto, Kouhei; Uzawa, Shigeyuki, Exposure apparatus, pressure control method for the same, and device manufacturing method.
  11. Randolph, Steven; Chandler, Clive D., High selectivity, low damage electron-beam delineation etch.
  12. Fujimoto, Masashi, Image processing alignment method and method of manufacturing semiconductor device.
  13. Sato, Yoshimichi; Ikeda, Mitsuji; Sasajima, Fumihiro, Image processing system and scanning electron microscope.
  14. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing DOEs of GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells.
  15. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells with first DOE including tip-to-side short configured fill cells and second DOE including chamfer short configured fill cells.
  16. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells.
  17. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including metal island open configured fill cells.
  18. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells.
  19. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells.
  20. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configured fill cells.
  21. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including metal island open configured fill cells.
  22. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including chamfer short configured fill cells.
  23. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including corner short configured fill cells.
  24. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including merged-via configured fill cells.
  25. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including metal island open configured fill cells.
  26. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-tip short configured fill cells.
  27. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit including NCEM-Enabled, tip-to-tip gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates.
  28. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit including NCEM-enabled, corner gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates.
  29. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Integrated circuit including NCEM-enabled, diagonal gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates.
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  41. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage.
  42. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one chamfer short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective chamfer short, corner short, and via open test areas.
  43. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one side-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective side-to-side short, corner short, and via open test areas.
  44. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and corner short test areas.
  45. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and via open test areas.
  46. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakages, and at least one via respective tip-to-tip short, side-to-side short, and via open test areas.
  47. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and chamfer short test areas.
  48. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side sort, and corner short test areas.
  49. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage.
  50. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas.
  51. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage.
  52. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Method for processing a semiconductor water using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, side to side short, and chamfer short test areas.
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  71. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells.
  72. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells.
  73. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including metal island open configured fill cells.
  74. Lam, Stephen; Ciplickas, Dennis; Brozek, Tomasz; Cheng, Jeremy; Comensoli, Simone; De, Indranil; Doong, Kelvin; Eisenmann, Hans; Fiscus, Timothy; Haigh, Jonathan; Hess, Christopher; Kibarian, John; Lee, Sherry; Liao, Marci; Lin, Sheng-Che; Matsuhashi, Hideki; Michaels, Kimon; O'Sullivan, Conor; Rauscher, Markus; Rovner, Vyacheslav; Strojwas, Andrzej; Strojwas, Marcin; Taylor, Carl; Vallishayee, Rakesh; Weiland, Larg; Yokoyama, Nobuharu, Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including stitch open configured fill cells.
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