초록

Expansion of the bandwidth of a wideband CMOS data amplifier is accomplished using various combinations of shunt peaking, series peaking, and miller capacitance cancellation. These various combinations are employed in any of the amplifier input stage, in intermediate stages, or in the last stage.

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What is claimed is: 1. An amplifier stage, comprising: a current source; a first differential transistor having a source, gate, and drain, wherein the source of the first differential transistor is coupled to the current source; a second differential transistor having a source, gate, and drain, w

What is claimed is: 1. An amplifier stage, comprising: a current source; a first differential transistor having a source, gate, and drain, wherein the source of the first differential transistor is coupled to the current source; a second differential transistor having a source, gate, and drain, wherein the source of the second differential transistor is coupled to the current source; a first output impedance having positive and negative ends, wherein the negative end of the first output impedance is coupled to the drain of the first differential transistor and wherein the first output impedance includes a first shunt peaking inductor; a second output impedance having positive and negative ends, wherein the negative end of the second output impedance is coupled to the drain of the second differential transistor and wherein the second output impedance includes a second shunt peaking inductor; a first miller capacitance cancellation capacitor having a positive and negative ends, wherein the positive end of the first miller capacitance cancellation capacitor is coupled to the drain of the second differential transistor, and wherein the negative end of the first miller capacitance cancellation capacitor is coupled to the gate of the first differential transistor; and a second miller capacitance cancellation capacitor having a positive and negative ends, wherein the positive end of the second miller capacitance cancellation capacitor is coupled to the drain of the first differential transistor, and wherein the negative end of the second miller capacitance cancellation capacitor is coupled to the gate of the second differential transistor. 2. The amplifier stage of claim 1, wherein: the first output impedance includes a first output resistor connected in series with the first shunt inductor; and the second output impedance includes a second output resistor connected in series with the second shunt inductor. 3. The amplifier stage of claim 1, wherein: the current source comprises a current source transistor having a gate, source, and drain; and the gate of the current source transistor is coupled to a bias voltage. 4. The amplifier stage of claim 3, wherein: the first and second differential transistors and the current source transistor comprise NMOS transistors or PMOS transistors. 5. The amplifier stage of claim 1, wherein: the positive end of the first output impedance is coupled to a voltage supply; and the positive end of the second output impedance is coupled to the voltage supply. 6. An amplifier stage, comprising: a current source; a first differential transistor having a source, gate, and drain, wherein the source of the first differential transistor is coupled to the current source; a second differential transistor having a source, gate, and drain, wherein the source of the second differential transistor is coupled to the current source; a first series peaking inductor having positive and negative ends, wherein the negative end of the first series peaking inductor is coupled to the gate of the first differential transistor; a second series peaking inductor having positive and negative ends, wherein the negative end of the second series peaking inductor is coupled to the gate of the second differential transistor; a first miller capacitance cancellation capacitor having positive and negative ends, wherein the positive end of the first miller capacitance cancellation capacitor is coupled to the drain of the second differential transistor, and wherein the negative end of the first miller capacitance cancellation capacitor is coupled to the gate of the first differential transistor; and a second miller capacitance cancellation capacitor having positive and negative ends, wherein the positive end of the second miller capacitance cancellation capacitor is coupled to the drain of the first differential transistor, and wherein the negative end of the second miller capacitance cancellation capacitor is coupled to the gate of the second differential transistor. 7. The amplifier stage of claim 6, wherein: the current source comprises a current source transistor having a gate, source, and drain; and the gate of the current source transistor is coupled to a bias voltage. 8. The amplifier stage of claim 7, wherein: the first and second differential transistors and the current source transistor comprise NMOS transistors. 9. The amplifier stage of claim 7, wherein: the first and second differential transistors and the current source transistor comprise PMOS transistors. 10. An amplifier stage, comprising: a current source; a first differential transistor having a source, gate, and drain, wherein the source of the first differential transistor is coupled to the current source; a second differential transistor having a source, gate, and drain, wherein the source of the second differential transistor is coupled to the current source; a first output resistor having positive and negative ends, wherein the negative end of the first output resistor is coupled to the drain of the first differential transistor; a second output resistor having positive and negative ends, wherein the negative end of the second output resistor is coupled to the drain of the second differential transistor; a first shunt peaking inductor having positive and negative ends, wherein the negative end of the first shunt peaking inductor is coupled to the positive end of the first output resistor; a second shunt peaking inductor having positive and negative ends, wherein the negative end of the second shunt peaking inductor is coupled to the positive end of the second output resistor; a first miller capacitance cancellation capacitor having positive and negative ends, wherein the positive end of the first miller capacitance cancellation capacitor is coupled to the drain of the second differential transistor, and wherein the negative end of the first miller capacitance cancellation capacitor is coupled to the gate of the first differential transistor; and a second miller capacitance cancellation capacitor having positive and negative ends, wherein the positive end of the second miller capacitance cancellation capacitor is coupled to the drain of the first differential transistor, and wherein the negative end of the second miller capacitance cancellation capacitor is coupled to the gate of the second differential transistor. 11. The amplifier stage of claim 10, wherein: the current source comprises a current source transistor having a gate, source, and drain; and the gate of the current source transistor is coupled to a bias voltage. 12. The amplifier stage of claim 11, wherein: the first and second differential transistors and the current source transistor comprise NMOS transistors. 13. The amplifier stage of claim 11, wherein: the first and second differential transistors and the current source transistor comprise PMOS transistors. 14. A multi-stage differential amplifier, comprising: a first amplifier stage, that includes a first differential transistor having a first source, a first gate, and a first drain, and a second differential transistor having a second source, a second gate, and a second drain, having a positive signal input, a negative signal input, a positive signal output, and a negative signal output; a second amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output; wherein the positive signal output of the first amplifier stage is coupled to the positive signal input of the second amplifier stage, and wherein the negative signal output of the first amplifier stage is coupled to the negative signal input of the second amplifier stage; wherein the first amplifier stage includes a first pair of series peaking inductors, a first pair of shunt peaking inductors, and a first pair of miller capacitance cancellation capacitors; and wherein a first miller capacitance cancellation capacitor, of the first pair of miller capacitance cancellation capacitors, having positive and negative ends, wherein the positive end of the first miller capacitance cancellation capacitor is coupled to the second drain of the second differential transistor, and wherein the negative end of the first miller capacitance cancellation capacitor is coupled to the first gate of the first differential transistor; wherein a second miller capacitance cancellation capacitor, of the first pair of miller capacitance cancellation capacitors, having positive and negative ends, wherein the positive end of the second miller capacitance cancellation capacitor is coupled to the first drain of the first differential transistor, and wherein the negative end of the second miller capacitance cancellation capacitor is coupled to the second gate of the second differential transistor; wherein the second amplifier stage includes a second pair of series peaking inductors and a second pair of shunt peaking inductors. 15. The multi-stage differential amplifier of claim 14, further comprising: a third amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output; wherein the positive signal output of the second amplifier stage is coupled to the positive signal input of the third amplifier stage, and wherein the negative signal output of the second amplifier stage is coupled to the negative signal input of the third amplifier stage; and wherein the third amplifier stage includes a third pair of series peaking inductors, a third pair of shunt peaking inductors, and a second pair of miller capacitance cancellation capacitors. 16. The multi-stage differential amplifier of claim 15, further comprising: a fourth amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output; wherein the positive signal output of the third amplifier stage is coupled to the positive signal input of the fourth amplifier stage, and wherein the negative signal output of the third amplifier stage is coupled to the negative signal input of the fourth amplifier stage; and wherein the fourth amplifier stage includes a fourth pair of series peaking inductors and a third pair of miller capacitance cancellation capacitors. 17. The multi-stage differential amplifier of claim 16, further comprising: a fifth amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output; wherein the positive signal output of the fourth amplifier stage is coupled to the positive signal input of the fifth amplifier stage, and wherein the negative signal output of the fourth amplifier stage is coupled to the negative signal input of the fifth amplifier stage; and wherein the fifth amplifier stage includes a fourth third pair of shunt peaking inductors. 18. The multi-stage differential amplifier of claim 17, further comprising: a sixth amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output; wherein the positive signal output of the fifth amplifier stage is coupled to the positive signal input of the sixth amplifier stage, and wherein the negative signal output of the fifth amplifier stage is coupled to the negative signal input of the sixth amplifier stage. 19. The multi-stage differential amplifier of claim 14, wherein: each shunt peaking inductor of the first pair of shunt peaking inductors is coupled in series with a corresponding output resistor. 20. The multi-stage differential amplifier of claim 14, wherein: each shunt peaking inductor of the second pair of shunt peaking inductors is coupled in series with a corresponding output resistor. 21. The multi-stage differential amplifier of claim 14, wherein: at least one of the first amplifier stage and the second amplifier stage includes: a current source; a first differential transistor having a source, gate, and drain, wherein the source of the first differential transistor is coupled to the current source; and a second differential transistor having a source, gate, and drain, wherein the source of the second differential transistor is coupled to the current source. 22. The multi-stage differential amplifier of claim 21, wherein: the current source comprises a current source transistor having a gate, source, and drain; and the gate of the current source transistor is coupled to a bias voltage. 23. The multi-stage differential amplifier of claim 22, wherein: the first and second differential transistors and the current source transistor comprise NMOS transistors. 24. The multi-stage differential amplifier of claim 22, wherein: the first and second differential transistors and the current source transistor comprise PMOS transistors. 25. A multi-stage differential amplifier, comprising: a first amplifier stage, that includes a first differential transistor having a first source, a first gate, and a first drain, and a second differential transistor having a second source, a second gate, and a second drain, having a positive signal input, a negative signal input, a positive signal output, and a negative signal output; a second amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output; wherein the positive signal output of the first amplifier stage is coupled to the positive signal input of the second amplifier stage, and wherein the negative signal output of the first amplifier stage is coupled to the negative signal input of the second amplifier stage; wherein the first amplifier stage includes a first pair of series peaking inductors, a first pair of shunt peaking inductors, and a first pair of miller capacitance cancellation capacitors; wherein a first miller capacitance cancellation capacitor, of the first pair of miller capacitance cancellation capacitors, having positive and negative ends, wherein the positive end of the first miller capacitance cancellation capacitor is coupled to the second drain of the second differential transistor, and wherein the negative end of the first miller capacitance cancellation capacitor is coupled to the first gate of the first differential transistor; wherein a second miller capacitance cancellation capacitor, of the first pair of miller capacitance cancellation capacitors, having positive and negative ends, wherein the positive end of the second miller capacitance cancellation capacitor is coupled to the first drain of the first differential transistor, and wherein the negative end of the second miller capacitance cancellation capacitor is coupled to the second gate of the second differential transistor; wherein each shunt peaking inductor of the first pair of shunt peaking inductors is coupled in series with a corresponding output resistor; wherein the second amplifier stage includes a second pair of series peaking inductors and a second pair of shunt peaking inductors; wherein each shunt peaking inductor of the second pair of shunt peaking inductors is coupled in series with a corresponding output resistor; a third amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output; wherein the positive signal output of the second amplifier stage is coupled to the positive signal input of the third amplifier stage, and wherein the negative signal output of the second amplifier stage is coupled to the negative signal input of the third amplifier stage; wherein the third amplifier stage includes a third pair of series peaking inductors, a third pair of shunt peaking inductors, and a second pair of miller capacitance cancellation capacitors; and wherein each shunt peaking inductor of the third pair of shunt peaking inductors is coupled in series with a corresponding output resistor. 26. The multi-stage differential amplifier of claim 25, wherein: at least one of the first amplifier stage and the second amplifier stage includes: a current source; a first differential transistor having a source, gate, and drain, wherein the source of the first differential transistor is coupled to the current source; and a second differential transistor having a source, gate, and drain, wherein the source of the second differential transistor is coupled to the current source. 27. The multi-stage differential amplifier of claim 26, wherein: the current source comprises a current source transistor having a gate, source, and drain; and the gate of the current source transistor is coupled to a bias voltage. 28. The multi-stage differential amplifier of claim 27, wherein: the first and second differential transistors and the current source transistor comprise NMOS transistors. 29. The multi-stage differential amplifier of claim 27, wherein: the first and second differential transistors and the current source transistor comprise PMOS transistors.