최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0237079 (2002-09-09) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 56 인용 특허 : 355 |
The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module,
The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.
What is claimed is: 1. An integral capacitor comprising: a power plane having a power surface and a power periphery, the power plane coupling power to signals of an integrated circuit operating at a fundamental frequency; a first ground plane having a first ground surface and a first ground periph
What is claimed is: 1. An integral capacitor comprising: a power plane having a power surface and a power periphery, the power plane coupling power to signals of an integrated circuit operating at a fundamental frequency; a first ground plane having a first ground surface and a first ground periphery, the first ground plane coupling ground to the signals, the first ground plane being separated from the power plane by a first distance, the first ground surface being larger than the power surface; the first ground periphery extending at least a second distance from the power periphery, the second distance being at least larger than N times the first distance; and a dielectric layer formed between the power plane and the first ground plane. 2. The integral capacitor of claim 1 further comprising: a second ground plane having a second ground surface and a second ground periphery, the second ground plane being separated from the power plane by the third distance; the second ground surface being larger than the power surface and the second ground periphery extending at least a fourth distance from the power periphery; the fourth distance being at least larger than M times the third distance, the second ground plane being coupled to the first ground plane by a via chain connecting a first plurality of vias located around the first ground periphery to a second plurality of vias located around the second ground periphery; and the first and second pluralities of vias having adjacent vias, the adjacent vias being spaced apart by a via distance that is smaller than a quarter wavelength of the fundamental frequency. 3. The integral capacitor of claim 1 wherein the dielectric layer is made of a dielectric material having a high dielectric constant. 4. The integral capacitor of claim 1 wherein N is an integer ranging from 1 to 20. 5. The integral capacitor of claim 1 wherein M is an integer ranging from 1 to 20. 6. The integral capacitor of claim 1 wherein the first plurality of vias having electrical contact to a plurality of adjacent contacts, the adjacent contacts being spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency. 7. The integral capacitor of claim 6 wherein the contacts are ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins. 8. The integral capacitor of claim 1 further comprises a contact array to connect to at least the first ground plane and the power plane. 9. The integral capacitor of claim 8 wherein the contact array is one of a C4 bump array, a BGA ball array, and a FCPGA pin array. 10. The integral capacitor of claim 9 wherein the ground plane has a plurality of adjacent contacts, the adjacent contacts being ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins and spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency. 11. A packaged device comprising: a die containing an integrated circuit; a plurality of controlled collapse chip connection (C4) bumps attaching the die to a substrate; and an integral capacitor attaching to the die to reduce radiation, the integral capacitor comprising: a power plane having a power surface and a power periphery, the power plane coupling power to signals of an integrated circuit operating at a fundamental frequency, a first ground plane having a first ground surface and a first ground periphery, the first ground plane coupling ground to the signals, the first ground plane being separated from the power plane by a first distance, the first ground surface being larger than the power surface and the first ground periphery extending at least a second distance from the power periphery, the second distance being at least larger than N times the first distance, and a dielectric layer formed between the power plane and the first ground plane. 12. The packaged device of claim 11 wherein the integral capacitor further comprising: a second ground plane having a second ground surface and a second ground periphery, the second ground plane being separated from the power plane by the third distance, the second ground surface being larger than the power surface and the second ground periphery extending at least a fourth distance from the power periphery, the fourth distance being at least larger than M times the third distance, the second ground plane being coupled to the first ground plane by a via chain connecting a first plurality of vias located around the first ground periphery to a second plurality of vias located around the second ground periphery, the first and second pluralities of vias having adjacent vias, the adjacent vias being spaced apart by a via distance that is smaller than a quarter wavelength of the fundamental frequency. 13. The packaged device of claim 12 wherein the dielectric layer is made of a dielectric material having a high dielectric constant. 14. The packaged device of claim 11 wherein N is an integer ranging from 1 to 20. 15. The packaged device of claim 11 wherein M is an integer ranging from 1 to 20. 16. The packaged device of claim 11 wherein the first plurality of vias having electrical contact to a plurality of adjacent contacts, the adjacent contacts being spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency. 17. The packaged device of claim 16 wherein the contacts are ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins. 18. The packaged device of claim 11 wherein the integral capacitor further comprises a contact array to connect to at least the first ground plane and the power plane. 19. The packaged device of claim 18 wherein the contact array is one of a C4) bump array, a BGA ball array, and a FCPGA pin array. 20. The packaged device of claim 19 wherein the ground plane has a plurality 15 of adjacent contacts, the adjacent contacts being ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins and spaced apart by a contact distance that is smaller than a quarter, wavelength of the fundamental frequency. 21. A method comprising: coupling power to signals of an integrated circuit operating at a fundamental frequency by a power plane having a power surface and a power periphery; coupling ground to the signals by a first ground plane having a first ground surface 5 and a first ground periphery, the first ground plane being separated from the power plane by a first distance, the first ground surface being larger than the power surface and the first ground periphery extending at least a second distance from the power periphery, the second distance being at least larger than N times the first distance; and forming a dielectric layer between the power plane and the first ground plane. 22. The method of claim 21 further comprising: coupling a second ground plane to the first ground plane by a via chain, the second ground plane having a second ground surface and a second ground periphery, the second ground plane being separated from the power plane by the third distance, the second ground surface being larger than the power surface and the second ground periphery extending at least a fourth distance from the power periphery, the fourth distance being at least larger than M times the third distance, the via chain connecting a first plurality of vias located around the first ground periphery to a second plurality of vias located around the second ground periphery, the first and second pluralities of vias having adjacent vias, the adjacent vias being spaced apart by a via distance that is smaller than a quarter wavelength of the fundamental frequency. 23. The method of claim 22 wherein the dielectric layer is made of a dielectric material having a high dielectric constant. 24. A method of claim 21 wherein N is an integer ranging from 1 to 20. 25. The method of claim 21 wherein M is an integer ranging from 1 to 20. 26. The method of claim 21 wherein the first plurality of vias having electrical contact to a plurality of adjacent contacts, the adjacent contacts being spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency. 27. The method of claim 26 wherein the contacts are ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins. 28. The method of claim 21 further comprises connecting to at least the first ground plane and the power plane by a contact array. 29. The method of claim 28 wherein the contact array is one of a C4 bump array, a BGA ball array, and a FCPGA pin array. 30. The method of claim 29 wherein the ground plane has a plurality of adjacent contacts, the adjacent contacts being ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins and spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency. 31. An energy conditioner comprising; a first pathway having a first surface and a first perimeter, and the first pathway coupled to an integrated circuit; a second pathway having a second surface and a second perimeter, and the second pathway coupled to the integrated circuit; the second pathway being separated from the first pathway by a first distance; the second surface being larger than the first surface; the second perimeter extending at least a second distance from the first perimeter; the second distance being at least larger than a number times the first distance; and a dielectric layer formed between the first pathway and the second pathway. 32. An enclosure comprising: a power plane having a power surface and a power periphery, the power plane coupling power to signals of an integrated circuit operating at a fundamental frequency; and first and second ground planes having first and second ground surfaces and first and second ground peripheries, the first and second ground planes coupling ground to the signals, the first and second ground planes being separated from the power plane by first and second distances, respectively, the first and second ground surfaces being larger than the power surface, the first and second ground peripheries extending at least third and fourth distances from the power peppery, respectively, the third and fourth distances being N and M times larger than the first and second distances, respectively. 33. The enclosure of claim 32 wherein the first and second ground planes have first and second pluralities of vias located around the first and second ground peripheries, respectively, and outside the power periphery, the first and second pluralities of vias having adjacent vias, the adjacent vias being spaced apart by a via distance that is smaller than a quarter wavelength of the fundamental frequency, the first and second pluralities of vias being connected by a via chain. 34. The enclosure of claim 33 wherein the signals are on a signal plane located between the power plane and the second ground plane. 35. The enclosure of claim 32 wherein N is an integer ranging from 1 to 20. 36. The enclosure of claim 32 wherein M is an integer ranging from 1 to 20. 37. The enclosure of claim 32 wherein the first plurality of vias having electrical contact to a plurality of adjacent contacts, the adjacent contacts being spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency. 38. The enclosure of claim 37 wherein the contacts are ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins. 39. The enclosure of claim 32 further comprises a contact array to connect to at least the first ground plane and the power plane. 40. The enclosure of claim 39 wherein the contact array is one of a C4 bump array, a BGA ball array, and a FCPGA pin array. 41. The enclosure of claim 40 wherein the ground plane has a plurality of adjacent contacts, the adjacent contacts being ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins and spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency. 42. A packaged device comprising: a die containing an integrated circuit having signals operating at a fundamental frequency; a plurality of controlled collapse chip connection (C4) bumps attaching the die to a substrate; and an enclosure attaching to the die to reduce radiation, the enclosure comprising: a power plane having a power surface and a power periphery, the power plane coupling power to the signals of the integrated circuit, and first and second ground planes having first and second ground surfaces and first and second ground peripheries, the first and second ground planes coupling ground to the signals, the first and second ground planes being separated from the power plane by first and second distances, respectively, the first and second ground surfaces being larger than the power surface, the first and second ground peripheries extending at least third and fourth distances from the power periphery, respectively, the third and fourth distances being N and M times larger than the first and second distances, respectively. 43. The packaged device of claim 42 wherein the first and second ground planes have first and second pluralities of vias located around the first and second ground peripheries, respectively, and outside the power periphery, the first and second pluralities of vias having adjacent vias, the adjacent vias being spaced apart by a via distance that is smaller than a quarter wavelength of the fundamental frequency, the first and second pluralities of vias being connected by a via chain. 44. The packaged device of claim 43 wherein the signals are on a signal plane located between the power plane and the second ground plane. 45. The packaged device of claim 42 wherein N is an integer ranging from 1 to 20. 46. The packaged device of claim 42 wherein M is an integer ranging from 1 to 20. 47. The packaged device of claim 42 wherein the first plurality of vias having electrical contact to a plurality of adjacent contacts, the adjacent contacts being spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency. 48. The packaged device of claim 47 wherein the contacts are ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins. 49. The packaged device of claim 42 wherein the enclosure further comprises a contact array to connect to at least the first ground plane and the power plane. 50. The packaged device of claim 49 wherein the contact array is one of a C4 bump array, a BGA ball array, and a FCPGA pin array. 51. The packaged device of claim 50 wherein the ground plane has a plurality of adjacent contacts, the adjacent contacts being ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins and spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency. 52. A method comprising: coupling power to signals of an integrated circuit operating at a fundamental frequency by a power plane having a power surface and a power periphery; and coupling pound to the signals by first and second ground planes having first and second ground surfaces and first and second ground peripheries, the first and second ground planes being separated from the power plane by first and second distances, respectively, the first and second ground surfaces being larger than the power surface, the first and second ground peripheries extending at least third and fourth distances from the power periphery, respectively, the third and fourth distances being N and M times larger than the first and second distances, respectively. 53. The method of claim 52 wherein the first and second ground planes have first and second pluralities of vias located around the first and second ground peripheries, respectively, and outside the power periphery, the first and second pluralities of vias having adjacent vias, the adjacent vias being spaced apart by a via distance that is smaller than a quarter wavelength of the fundamental frequency, the first and second pluralities of vias being connected by a via chain. 54. The method of claim 53 wherein the signals are on a signal plane located between the power plane and the second ground plane. 55. The method of claim 52 wherein N is an integer ranging from 1 to 20. 56. The method of claim 52 wherein M is an integer ranging from 1 to 20. 57. The method of claim 52 wherein the first plurality of vias having electrical contact to a plurality of adjacent contacts, the adjacent contacts being spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency. 58. The method of claim 57 wherein the contacts are ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins. 59. The method of claim 52 further comprises connecting to at least the first ground plane and the power plane by a contact array. 60. The method of claim 59 wherein the contact array is one of a C4 bump array, a BGA ball array, and a FCPGA pin array. 61. The method of claim 60 wherein the ground plane has a plurality of adjacent contacts, the adjacent contacts being ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins and spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.
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