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Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0996163 (2004-11-23)
발명자 / 주소
  • Swan,Johanna M.
  • Natarajan,Bala
  • Chiang,Chien
  • Atwood,Greg
  • Rao,Valluri R.
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor &
인용정보 피인용 횟수 : 7  인용 특허 : 91

초록

An electronic assembly is assembled by stacking two or more integrated circuit dies on top of one another. Prior to singulation, an opening is laser-drilled into an upper die, and subsequently filled with a conductive member. The conductive member is located on a lower die and interconnects integrat

대표청구항

What is claimed is: 1. An electronic assembly, comprising: a first substrate having a lower surface and an upper surface; a plurality of transistors formed on the upper surface of the first substrate; an integrated circuit formed above the transistors and connected to the transistors, the first su

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이 특허를 인용한 특허 (7)

  1. Reed, Paul A.; Black, Bryan P., Method for incorporating existing silicon die into 3D integrated stack.
  2. Pratt, David, Redistribution layers for microfeature workpieces, and associated systems and methods.
  3. Pratt, David, Redistribution layers for microfeature workpieces, and associated systems and methods.
  4. Pratt, David, Redistribution layers for microfeature workpieces, and associated systems and methods.
  5. Fürgut, Edward; Mahler, Joachim; Bauer, Michael, Semiconductor device including electronic component coupled to a backside of a chip.
  6. Umemoto,Mitsuo; Kameyama,Kojiro; Suzuki,Akira, Semiconductor device with a peeling prevention layer.
  7. Park, Yeun-Sang; Park, Byung-Lyul; Kang, SungHee; Kim, Taeseong; Moon, Kwangjin; Bang, Sukchul, Semiconductor devices.
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