초록 ▼

A programmable logic device (PLD) includes dynamic lookup table (LUT) circuits, an interconnect structure implemented in either dynamic or static logic, and optional static logic circuits. Each dynamic LUT circuit has paired true and complement input terminals and provides to the interconnect struct

A programmable logic device (PLD) includes dynamic lookup table (LUT) circuits, an interconnect structure implemented in either dynamic or static logic, and optional static logic circuits. Each dynamic LUT circuit has paired true and complement input terminals and provides to the interconnect structure both true and complement output signals pre-charged to a first known value. In some embodiments, the LUT circuits are self-resetting circuits that detect when the paired input signals are valid and evaluate the LUT output values at that time. Once a valid LUT output value has been produced, the LUT resets itself in anticipation of the next valid input condition. In some embodiments, the LUT circuits are implemented using clocked dynamic logic. Routing multiplexers in the interconnect structure can be static or dynamic logic, optionally skewed. Clocked LUTs and routing multiplexers use either of two clock phases under the control of configuration memory cells of the PLD.

대표청구항 ▼

What is claimed is: 1. A programmable logic device (PLD), comprising: a plurality of dynamic lookup table (LUT) circuits, each dynamic LUT circuit comprising a plurality of paired true and complement input terminals and a pair of true and complement output terminals, each of the true and complement

What is claimed is: 1. A programmable logic device (PLD), comprising: a plurality of dynamic lookup table (LUT) circuits, each dynamic LUT circuit comprising a plurality of paired true and complement input terminals and a pair of true and complement output terminals, each of the true and complement output terminals being configured and arranged to provide a dynamic output signal pre-charged to a first known value; and an interconnect structure programmably interconnecting the dynamic LUT circuits one to another via the true and complement input terminals and the true and complement output terminals of the dynamic LUT circuits. 2. The PLD of claim 1, wherein the first known value is a high value. 3. The PLD of claim 1, further comprising a plurality of flip-flops, each flip-flop being programmably coupled between one of the true and complement output terminals of a corresponding dynamic LUT circuit and the interconnect structure. 4. The PLD of claim 1, wherein the plurality of paired true and complement input terminals comprises six true input terminals and six complement input terminals. 5. The PLD of claim 1, wherein the PLD comprises a field programmable gate array (FPGA). 6. The PLD of claim 1, wherein the interconnect structure comprises a plurality of routing multiplexers, each routing multiplexer comprising skewed logic configured and arranged to pass a change in value from the first known value to a second known value more quickly than a change in value from the second known value to the first known value. 7. The PLD of claim 6, wherein the first known value is a high value and the second known value is a low value. 8. The PLD of claim 1, wherein each dynamic LUT circuit comprises skewed logic configured and arranged to pass a change in value from the first known value to a second known value more quickly than a change in value from the second known value to the first known value. 9. The PLD of claim 8, wherein the first known value is a high value and the second known value is a low value. 10. The PLD of claim 1, wherein at least one of the dynamic LUT circuits comprises a self-resetting LUT circuit. 11. The PLD of claim 10, further comprising: a plurality of flip-flop interface circuits, each flip-flop interface circuit having an input terminal coupled to one of the true and complement output terminals of a corresponding one of the dynamic LUT circuits, a clock input terminal, and an output terminal; and a plurality of flip-flops, each flip-flop having a data input terminal coupled to the output terminal of a corresponding one of the flip-flop interface circuits and further having a pair of true and complement output terminals coupled to the interconnect structure. 12. The PLD of claim 11, wherein each flip-flop interface circuit comprises a latch coupled between the input terminal and the output terminal of the flip-flop interface circuit, each latch having a pre-charge input terminal coupled to the clock input terminal of a corresponding one of the flip-flops. 13. The PLD of claim 10, wherein the self-resetting LUT circuit comprises: a memory array comprising a plurality of bitlines, a plurality of input terminals coupled to the interconnect structure, and a plurality of output terminals; a pre-charge generator circuit having a plurality of input terminals coupled to the interconnect structure and a pre-charge output terminal; a bitline pre-charge circuit coupled to the bitlines, the bitline pre-charge circuit having a pre-charge input terminal coupled to the pre-charge output terminal of the pre-charge generator circuit and further having a reset input terminal; and an output circuit having a plurality of input terminals coupled to the output terminals of the memory array, true and complement output terminals coupled to the true and complement output terminals of the self-resetting LUT circuit, and a reset output terminal coupled to the reset input terminal of the bitline pre-charge circuit. 14. The PLD of claim 13, wherein the output circuit comprises an exclusive OR gate having input terminals coupled to the true and complement output terminals of the output LUT circuit and further having an output terminal coupled to the reset output terminal of the output circuit. 15. The PLD of claim 13, wherein the self-resetting LUT circuit further comprises: a decoder circuit coupled between the interconnect structure and the memory array, the decoder circuit comprising a decoder interface circuit coupled to the interconnect structure and a decoder coupled between the decoder interface circuit and the memory array, wherein the decoder interface circuit comprises a plurality of latches coupled between the interconnect structure and the decoder, each of the latches having a reset input terminal coupled to the reset output terminal of the output circuit. 16. The PLD of claim 15, wherein: the memory array further comprises an array of memory cells coupled to the bitlines and a read multiplexer coupled between the bitlines and the output terminals of the memory array; the decoder circuit is configured and arranged to more slowly pass first input signals from a first plurality of input terminals, and is further configured and arranged to more quickly pass second input signals from a second plurality of input terminals; the decoder circuit is configured and arranged to provide from the first input signals a plurality of first decoded signals to the array of memory cells; and the decoder circuit is further configured and arranged to provide from the second input signals a plurality of second decoded signals to the read multiplexer. 17. The PLD of claim 16, wherein the first plurality of input terminals of the decoder circuit comprise eight paired true and complement input terminals and the second plurality of input terminals of the decoder circuit comprise four paired true and complement input terminals. 18. The PLD of claim 16, wherein the read multiplexer comprises two paired output terminals configured and arranged to provide signals derived from two paired ones of the bitlines. 19. The PLD of claim 13, wherein the self-resetting LUT circuit further comprises: a read logic circuit coupled between the output terminals of the memory array and the input terminals of the output circuit, the read logic circuit having a pre-charge input terminal coupled to the pre-charge output terminal of the pre-charge generator circuit and further having a reset input terminal coupled to the reset output terminal of the output circuit. 20. The PLD of claim 1, wherein at least one of the dynamic LUT circuits comprises a clock input terminal, the PLD further comprising: a memory cell; and a clock multiplexer having an output terminal coupled to the clock input terminal of the at least one dynamic LUT circuit, a first data input terminal coupled to receive a first clock signal, a second data input terminal coupled to receive a second clock signal, and a select terminal coupled to the memory cell. 21. The PLD of claim 20, wherein the PLD comprises a field programmable gate array (FPGA), and the memory cell comprises a configuration memory cell of the FPGA. 22. The PLD of claim 1, wherein the interconnect structure comprises a plurality of routing multiplexers, and at least one of the routing multiplexers comprises a dynamic routing multiplexer having an output terminal configured and arranged to provide a dynamic output signal pre-charged to the first known value. 23. The PLD of claim 22, wherein the first known value is a high value. 24. The PLD of claim 22, wherein the dynamic routing multiplexer comprises a clock input terminal, the PLD further comprising: a memory cell; and a clock multiplexer having an output terminal coupled to the clock input terminal of the dynamic routing multiplexer, a first data input terminal coupled to receive a first clock signal, a second data input terminal coupled to receive a second clock signal, and a select terminal coupled to the memory cell. 25. The PLD of claim 24, wherein the PLD comprises a field programmable gate array (FPGA) and the memory cell comprises a configuration memory cell of the FPGA. 26. The PLD of claim 1, wherein the interconnect structure comprises a plurality of routing multiplexers coupled into pairs configured and arranged to pass paired true and complement output signals. 27. The PLD of claim 26, further comprising, for each pair of the routing multiplexers: a plurality of memory cells, each memory cell being coupled to each of the routing multiplexers in the pair of routing multiplexers. 28. The PLD of claim 27, wherein the PLD comprises a field programmable gate array (FPGA), and the memory cells comprise configuration memory cells of the FPGA. 29. The PLD of claim 26, wherein each of the routing multiplexers is configured and arranged to provide a dynamic output signal pre-charged to the first known value. 30. The PLD of claim 26, wherein each of the routing multiplexers is configured and arranged to provide a static output signal. 31. A programmable logic device (PLD), comprising: a plurality of programmable static logic circuits; a plurality of dynamic lookup table (LUT) circuits, each dynamic LUT circuit comprising a plurality of paired true and complement input terminals and a pair of true and complement output terminals, each of the true and complement output terminals being configured and arranged to provide a dynamic output signal pre-charged to a first known value; and an interconnect structure coupled to the dynamic LUT circuits via the true and complement input terminals and the true and complement output terminals of the dynamic LUT circuits and further coupled to the programmable static logic circuits. 32. The PLD of claim 31, wherein the plurality of programmable static logic circuits comprise a plurality of static LUT circuits. 33. The PLD of claim 31, wherein: the plurality of programmable static logic circuits are arranged to form a first column; the plurality of dynamic LUT circuits are arranged to form a second column; and the PLD comprises a row of columns that includes the first and second columns. 34. The PLD of claim 31, wherein the first known value is a high value. 35. The PLD of claim 31, further comprising a plurality of flip-flops, each flip-flop being programmably coupled between one of the true and complement output terminals of a corresponding dynamic LUT circuit and the interconnect structure. 36. The PLD of claim 31, wherein the PLD comprises a field programmable gate array (FPGA). 37. The PLD of claim 31, wherein the interconnect structure comprises a plurality of routing multiplexers, each routing multiplexer comprising skewed logic configured and arranged to pass a change in value from the first known value to a second known value more quickly than a change in value from the second known value to the first known value. 38. The PLD of claim 37, wherein the first known value is a high value and the second known value is a low value. 39. The PLD of claim 31, wherein each dynamic LUT circuit comprises skewed logic configured and arranged to pass a change in value from the first known value to a second known value more quickly than a change in value from the second known value to the first known value. 40. The PLD of claim 39, wherein the first known value is a high value and the second known value is a low value. 41. The PLD of claim 31, wherein at least one of the dynamic LUT circuits comprises a self-resetting LUT circuit. 42. The PLD of claim 41, further comprising: a plurality of flip-flop interface circuits, each flip-flop interface circuit having an input terminal coupled to one of the true and complement output terminals of a corresponding one of the dynamic LUT circuits, a clock input terminal, and an output terminal; and a plurality of flip-flops, each flip-flop having a data input terminal coupled to the output terminal of a corresponding one of the flip-flop interface circuits and further having a pair of true and complement output terminals coupled to the interconnect structure. 43. The PLD of claim 41, wherein the self-resetting LUT circuit comprises: a memory array comprising a plurality of bitlines, a plurality of input terminals coupled to the interconnect structure, and a plurality of output terminals; a pre-charge generator circuit having a plurality of input terminals coupled to the interconnect structure and a pre-charge output terminal; a bitline pre-charge circuit coupled to the bitlines, the bitline pre-charge circuit having a pre-charge input terminal coupled to the pre-charge output terminal of the pre-charge generator circuit and further having a reset input terminal; and an output circuit having a plurality of input terminals coupled to the output terminals of the memory array, true and complement output terminals coupled to the true and complement output terminals of the self-resetting LUT circuit, and a reset output terminal coupled to the reset input terminal of the bitline pre-charge circuit. 44. The PLD of claim 43, wherein the self-resetting LUT circuit further comprises: a decoder circuit coupled between the interconnect structure and the memory array, the decoder circuit comprising a decoder interface circuit coupled to the interconnect structure and a decoder coupled between the decoder interface circuit and the memory array, wherein the decoder interface circuit comprises a plurality of latches coupled between the interconnect structure and the decoder, each of the latches having a reset input terminal coupled to the reset output terminal of the output circuit. 45. The PLD of claim 44, wherein: the memory array further comprises an array of memory cells coupled to the bitlines and a read multiplexer coupled between the bitlines and the output terminals of the memory array; the decoder circuit is configured and arranged to more slowly pass first input signals from a first plurality of input terminals, and is further configured and arranged to more quickly pass second input signals from a second plurality of input terminals; the decoder circuit is configured and arranged to provide from the first input signals a plurality of first decoded signals to the array of memory cells; and the decoder circuit is further configured and arranged to provide from the second input signals a plurality of second decoded signals to the read multiplexer. 46. The PLD of claim 45, wherein the first plurality of input terminals of the decoder circuit comprise eight paired true and complement input terminals and the second plurality of input terminals of the decoder circuit comprise four paired true and complement input terminals. 47. The PLD of claim 45, wherein the read multiplexer comprises two paired output terminals configured and arranged to provide signals derived from two paired ones of the bitlines. 48. The PLD of claim 44, wherein the self-resetting LUT circuit further comprises: a read logic circuit coupled between the output terminals of the memory array and the input terminals of the output circuit, the read logic circuit having a pre-charge input terminal coupled to the pre-charge output terminal of the pre-charge generator circuit and further having a reset input terminal coupled to the reset output terminal of the output circuit. 49. The PLD of claim 31, wherein at least one of the dynamic LUT circuits comprises a clock input terminal, the PLD further comprising: a memory cell; and a clock multiplexer having an output terminal coupled to the clock input terminal of the at least one dynamic LUT circuit, a first data input terminal coupled to receive a first clock signal, a second data input terminal coupled to receive a second clock signal, and a select terminal coupled to the memory cell. 50. The PLD of claim 49, wherein the PLD comprises a field programmable gate array (FPGA), and the memory cell comprises a configuration memory cell of the FPGA. 51. The PLD of claim 31, wherein the interconnect structure comprises a plurality of routing multiplexers, and at least one of the routing multiplexers comprises a dynamic routing multiplexer having an output terminal configured and arranged to provide a dynamic output signal pre-charged to the first known value. 52. The PLD of claim 51, wherein the first known value is a high value. 53. The PLD of claim 51, wherein the dynamic routing multiplexer comprises a clock input terminal, the PLD further comprising: a memory cell; and a clock multiplexer having an output terminal coupled to the clock input terminal of the dynamic routing multiplexer, a first data input terminal coupled to receive a first clock signal, a second data input terminal coupled to receive a second clock signal, and a select terminal coupled to the memory cell. 54. The PLD of claim 53, wherein the PLD comprises a field programmable gate array (FPGA), and the memory cell comprises a configuration memory cell of the FPGA. 55. The PLD of claim 31, wherein the interconnect structure comprises a plurality of routing multiplexers coupled into pairs configured and arranged to pass paired true and complement output signals. 56. The PLD of claim 55, further comprising, for each pair of the routing multiplexers: a plurality of memory cells, each memory cell being coupled to each of the routing multiplexers in the pair of routing multiplexers. 57. The PLD of claim 56, wherein the PLD comprises a field programmable gate array (FPGA), and the memory cells comprise configuration memory cells of the FPGA. 58. The PLD of claim 55, wherein each of the routing multiplexers is configured and arranged to provide a dynamic output signal pre-charged to the first known value. 59. The PLD of claim 55, wherein each of the routing multiplexers is configured and arranged to provide a static output signal. 60. A programmable logic device (PLD), comprising: a plurality of dynamic lookup table (LUT) circuits, each dynamic LUT circuit comprising a plurality of paired true and complement input terminals and a pair of true and complement output terminals, each of the true and complement output terminals being configured and arranged to provide a dynamic output signal pre-charged to a first known value, each of the dynamic LUT circuits having a clock input terminal; an interconnect structure comprising a plurality of dynamic routing multiplexers programmably interconnecting the dynamic LUT circuits one to another via the true and complement input terminals and the true and complement output terminals of the dynamic LUT circuits, each dynamic routing multiplexer having a clock input terminal and further having an output terminal configured and arranged to provide a dynamic output signal pre-charged to the first known value; a plurality of first memory cells; and a plurality of clock multiplexers each having an output terminal coupled to the clock input terminal of an associated one of the dynamic LUT circuits and the dynamic routing multiplexers, a first data input terminal coupled to receive a first clock signal, a second data input terminal coupled to receive a second clock signal, and a select terminal coupled to an associated one of the first memory cells. 61. The PLD of claim 60, wherein the first known value is a high value. 62. The PLD of claim 60, further comprising a plurality of flip-flops, each flip-flop being programmably coupled between one of the true and complement output terminals of a corresponding dynamic LUT circuit and the interconnect structure. 63. The PLD of claim 60, wherein the plurality of paired true and complement input terminals comprises six true input terminals and six complement input terminals. 64. The PLD of claim 60, wherein the PLD comprises a field programmable gate array (FPGA), and the first memory cells comprise configuration memory cells of the FPGA. 65. The PLD of claim 60, wherein the dynamic routing multiplexers are coupled into pairs configured and arranged to pass paired true and complement output signals. 66. The PLD of claim 65, further comprising, for each pair of the dynamic routing multiplexers: a plurality of second memory cells, each second memory cell being coupled to each of the dynamic routing multiplexers in the pair of dynamic routing multiplexers. 67. The PLD of claim 66, wherein the PLD comprises a field programmable gate array (FPGA), and the second memory cells comprise configuration memory cells of the FPGA. 68. The PLD of claim 65, wherein each of the dynamic routing multiplexers is configured and arranged to provide a dynamic output signal pre-charged to the first known value. 69. The PLD of claim 60, wherein each of the dynamic routing multiplexers comprises skewed logic configured and arranged to pass a change in value from the first known value to a second known value more quickly than a change in value from the second known value to the first known value. 70. The PLD of claim 69, wherein the first known value is a high value and the second known value is a low value. 71. The PLD of claim 60, wherein each of the dynamic LUT circuits comprises skewed logic configured and arranged to pass a change in value from the first known value to a second known value more quickly than a change in value from the second known value to the first known value. 72. The PLD of claim 71, wherein the first known value is a high value and the second known value is a low value. 73. A self-resetting lookup table (LUT) circuit, comprising: a plurality of LUT input terminals comprising a plurality of paired true and complement input terminals; a memory array comprising a plurality of bitlines, a plurality of input terminals coupled to the LUT input terminals, and a plurality of output terminals; a pre-charge generator circuit having a plurality of input terminals coupled to the LUT input terminals and further having a pre-charge output terminal; a bitline pre-charge circuit coupled to the bitlines, the bitline pre-charge circuit having a pre-charge input terminal coupled to the pre-charge output terminal of the pre-charge generator circuit and further having a reset input terminal; and an output circuit having a plurality of input terminals coupled to the output terminals of the memory array, true and complement output terminals each configured and arranged to provide a dynamic output signal pre-charged to a first known value, and a reset output terminal coupled to the reset input terminal of the bitline pre-charge circuit. 74. The self-resetting LUT circuit of claim 73, wherein the first known value is a high value. 75. The self-resetting LUT circuit of claim 73, wherein: the plurality of paired true and complement input terminals comprises six true input terminals and six complement input terminals, and four of the true input terminals and four of the complement input terminals are coupled to the input terminals of the pre-charge generator circuit. 76. The self-resetting LUT circuit of claim 73, wherein the self-resetting LUT circuit forms a portion of a programmable logic device (PLD). 77. The self-resetting LUT circuit of claim 76, wherein the PLD comprises a field programmable gate array (FPGA). 78. The self-resetting LUT circuit of claim 73, wherein the output circuit comprises an exclusive OR gate having input terminals coupled to the true and complement output terminals of the output circuit and further having an output terminal coupled to the reset output terminal of the output circuit. 79. The self-resetting LUT circuit of claim 73, further comprising: a decoder circuit coupled between the LUT input terminals and the memory array, the decoder circuit comprising a decoder interface circuit coupled to the LUT input terminals and a decoder coupled between the decoder interface circuit and the memory array, wherein the decoder interface circuit comprises a plurality of latches coupled between the LUT input terminals and the input terminals of the decoder, each of the latches having a reset input terminal coupled to the reset output terminal of the output circuit. 80. The self-resetting LUT circuit of claim 73, wherein: the memory array further comprises an array of memory cells coupled to the bitlines and a read multiplexer coupled between the bitlines and the output terminals of the memory array; the decoder circuit is configured and arranged to more slowly pass first input signals from a first plurality of input terminals, and is further configured and arranged to more quickly pass second input signals from a second plurality of input terminals; the decoder circuit is configured and arranged to provide from the first input signals a plurality of first decoded signals to the array of memory cells; and the decoder circuit is further configured and arranged to provide from the second input signals a plurality of second decoded signals to the read multiplexer. 81. The self-resetting LUT circuit of claim 80, wherein the first plurality of input terminals of the decoder circuit comprise eight paired true and complement input terminals and the second plurality of input terminals of the decoder circuit comprise four paired true and complement input terminals. 82. The self-resetting LUT circuit of claim 80, wherein the read multiplexer comprises two paired output terminals configured and arranged to provide signals derived from two paired ones of the bitlines. 83. The self-resetting LUT circuit of claim 73, further comprising: a read logic circuit coupled between the output terminals of the memory array and the input terminals of the output circuit, the read logic circuit having a pre-charge input terminal coupled to the pre-charge output terminal of the pre-charge generator circuit and further having a reset input terminal coupled to the reset output terminal of the output circuit. 84. The self-resetting LUT circuit of claim 73, wherein the pre-charge generator circuit comprises skewed logic configured and arranged to pass a change in value on the LUT input terminals from the first known value to a second known value more quickly than a change in value from the second known value to the first known value. 85. The self-resetting LUT circuit of claim 84, wherein the first known value is a high value and the second known value is a low value. 86. The self-resetting LUT circuit of claim 73, wherein the output circuit comprises skewed logic configured and arranged to provide a change in value on the LUT output terminals from the first known value to a second known value more quickly than a change in value from the second known value to the first known value. 87. The self-resetting LUT circuit of claim 86, wherein the first known value is a high value and the second known value is a low value. 88. The self-resetting LUT circuit of claim 73, wherein: the self-resetting LUT circuit further comprises a decoder circuit coupled between the LUT input terminals and the memory array, and the decoder circuit comprises skewed logic configured and arranged to pass a change in value on the LUT input terminals from the first known value to a second known value more quickly than a change in value from the second known value to the first known value. 89. The self-resetting LUT circuit of claim 88, wherein the first known value is a high value and the second known value is a low value. 90. A programmable circuit, comprising: a true output terminal; a complement output terminal; a first plurality of pass transistors each having a first data terminal, a second data terminal coupled to the true output terminal, and a gate terminal; a second plurality of pass transistors each having a first data terminal, a second data terminal coupled to the complement output terminal, and a gate terminal; a plurality of memory cells, each memory cell being coupled to the gate terminal of one of the first plurality of pass transistors and further being coupled to the gate terminal of a corresponding one of the second plurality of pass transistors; and a first output buffer having an input terminal coupled to the true output terminal and a second output buffer having an input terminal coupled to the complement output terminal. 91. The programmable circuit of claim 90, wherein each of the first and second output buffers comprises skewed logic configured and arranged to pass a change in value from a first known value to a second known value more quickly than a change in value from the second known value to the first known value. 92. The programmable circuit of claim 91, wherein the first known value is a high value and the second known value is a low value. 93. The programmable circuit of claim 90, wherein: the first output buffer comprises a first pullup coupled to an output terminal of the first output buffer; the second output buffer comprises a second pullup coupled to an output terminal of the first output buffer; and each of the first and second pullups comprises a gate terminal coupled to a common clock input terminal. 94. The programmable circuit of claim 93, wherein each of the first and second output buffers comprises skewed logic configured and arranged to pass a change in value from a high value to a low value more quickly than a change in value from the low value to the high value. 95. The programmable circuit of claim 90, wherein the programmable circuit comprises a portion of an interconnect structure in a programmable logic device (PLD). 96. The programmable circuit of claim 95, wherein the PLD comprises a field programmable gate array (FPGA), and the memory cells comprise configuration memory cells of the FPGA.