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Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-011/34
출원번호 US-0863529 (2004-06-09)
발명자 / 주소
  • Eitan,Boaz
출원인 / 주소
  • Saifun Semiconductors LTD
대리인 / 주소
    Eitan Law Group
인용정보 피인용 횟수 : 30  인용 특허 : 163

초록

A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a nonconducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. A left and a r

대표청구항

What is claimed is: 1. A nitride read only memory (NROM) cell comprising: a charge trapping region comprising at least a nitride layer; a drain region and a source region; and a first and a second charge storage area within said nitride layer, said first charge storage area being close to said dra

이 특허에 인용된 특허 (163)

  1. Kimura Koichi,JPX ; Sawano Mitsuru,JPX, Array-type exposing device and flat type display incorporating light modulator and driving method thereof.
  2. Dadashev Oleg,ILX, Bit line control circuit for a memory array using 2-bit non-volatile memory cells.
  3. Wang, Fei; Foote, David K.; Park, Stephen K., Bit-line oxidation by removing ONO oxide prior to bit-line implant.
  4. Diaz Carlos H., Device and method of manufacture for protection against plasma charging damage in advanced MOS technologies.
  5. Hong Gary (Hsin TWX) Ko Joe (Hsinchu TWX), Device for preventing antenna effect on circuit.
  6. Liu David K. ; Wong Ting-wah, Device with embedded flash and EEPROM memories.
  7. Bergemont Albert ; Kalnitsky Alexander, EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming.
  8. Allen Bert L. (Los Altos CA) Forouhi A. Rahim (San Jose CA), EPROM with ultraviolet radiation transparent silicon nitride passivation layer.
  9. Kotecha, Harish N.; Noble, Jr., Wendell P.; Wiedman, III, Francis W., Electrically alterable double dense memory.
  10. Amin Alaaeldin A. M. (Dhahran CA SAX) Brennan ; Jr. James (Saratoga CA), Electrically reprogrammable EPROM cell with merged transistor and optimum area.
  11. Koyama Shoji (Tokyo JPX), Erasable, programmable read-only memory device.
  12. Matsuo Makoto,JPX ; Yokozawa Ayumi,JPX, Erasing method in nonvolatile semiconductor memory device.
  13. Cappelletti Paolo,ITX, FLASH-EPROM with embedded EEPROM.
  14. Schumann Steven J. (Sunnyvale CA) Hu James C. (Saratoga CA), Fabricating a narrow width EEPROM with single diffusion electrode formation.
  15. Mitchell Allan T. (Garland TX) Riemenschneider Bert R. (Murphy TX), Fabricating a single level merged EEPROM cell having an ONO memory stack substantially spaced from the source region.
  16. Freiberger Philip E. (Santa Clara CA) Yau Leopoldo D. (Portland OR) Pan Cheng-Sheng (Sunnyvale CA) Sery George E. (San Franciso CA), Fabrication of interpoly dielctric for EPROM-related technologies.
  17. Song Bok Nam,KRX, Flash EEPROM cell, method of manufacturing the same, method of programming and method of reading the same.
  18. Haddad Sameer S. (San Jose CA) Fang Hao (Cupertino CA), Flash EEPROM memory with improved discharge speed using substrate bias and method therefor.
  19. Mihnea Andrei ; Rudeck Paul J. ; Chen Chun, Flash memory cell.
  20. Yider Wu ; Jean Y. Yang ; Hidehiko Shiraiwa ; Che-Hoo Ng, Flash memory erase speed by fluorine implant or fluorination.
  21. Okazawa Takeshi,JPX, Flash memory including improved transistor cells and a method of programming the memory.
  22. Paterson James L. (Richardson TX) Haken Roger A. (Richardson TX), Floating gate memory with improved dielectric.
  23. Yiu Tom D. H. (Milpitas CA) Shone Fuchia (Hsinchu CA TWX) Lin Tien-Ler (Cupertino CA) Chen Ling (Sunnyvale CA), Floating gate or flash EPROM transistor array having contactless source and drain diffusions.
  24. Mitchell Allan T. (Garland TX) Tigelaar Howard L. (Allen TX), Four memory state EEPROM.
  25. Zheng, Wei; Randolph, Mark W.; Tripsas, Nicholas H.; Krivokapic, Zoran; Thomas, Jack F.; Ramsbey, Mark T., Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same.
  26. Wu Shye-Lin,TWX, High density flat cell mask ROM.
  27. Ransom Stephen A. (Huntingdon Valley PA) Stickel Tedd K. (Chalfont PA), High performance MESFET transistor for VLSI implementation.
  28. Hsu Sheng T. (Lawrenceville NJ) Hollingsworth Richard J. (Princeton NJ), High performance electrically alterable read-only memory (EAROM).
  29. Blanchard Richard A. (Sunnyvale CA) Choy Benedict C. K. (Campbell CA), High power MOS device and fabrication method therefor.
  30. Halliyal Arvind ; Ogle Robert B. ; Komori Hideki ; Au Kenneth, High temperature oxide deposition process for fabricating an ONO floating-gate electrode in a two bit EEPROM device.
  31. Harari Eliyahou (2320 Friars La. Los Altos CA 94022), Highly scalable dynamic RAM cell with self-signal amplification.
  32. Bell Antony G. (Sunnyvale CA), Insulated gate field-effect transistor read-only memory array.
  33. Hayes James A. (Mountain View CA), Insulated gate field-effect transistor read-only memory cell.
  34. Chang Yun,TWX ; Shone Fuchia,TWX ; Huang Chin-Yi,TWX ; Peng Nai chen,TWX, Interpoly dielectric process.
  35. Ko Joe (Hsinchu TWX) Hsu Bill (Hsinchu TWX), Layout design to eliminate process antenna effect.
  36. Pakkala William Frank ; Kekel Steven C. ; Du Bois Paul Louis ; Crawford Daniel Alexander ; Burnham Adam L., Load circuit having extended reverse voltage protection.
  37. Chang Shang-De (Fremont CA) Chang Jia-Hwang (Cupertino CA) Chow Edwin (Saratoga CA), Low voltage one transistor flash EEPROM cell using Fowler-Nordheim programming and erase.
  38. Kitamura Kenji,JPX ; Osanai Jun,JPX ; Koiwa Sumio,JPX, MOS semiconductor device.
  39. Egawa Yuichi (Tokyo JPX) Wada Toshio (Tokyo JPX) Iwasa Shoichi (Tokyo JPX), MOS-type semiconductor device and method of making the same.
  40. Irani Rustom F. (Santa Clara CA) Kazerounian Reza (Alameda CA) Nelson Mark Michael (Pocatello ID), Manufacturing method for ROM array with minimal band-to-band tunneling.
  41. Wolstenholme Graham (Boise ID) Bergemont Albert (San Jose CA) Shacham Etan (Cupertino CA), Memory array with field oxide islands eliminated and method.
  42. Liang Mong-Song (Milpitas CA) Lee Tien-Chiun (Sunnyvale CA), Memory cell having hot-hole injection erase mode.
  43. Bez Roberto,ITX ; Modelli Alberto,ITX, Memory device with a cell array in triple well, and related manufacturing process.
  44. Rajkanan Kamal (Melville NY) Multani Jagir S. (Dix Hills NY), Memory implant profile for improved channel shielding in electrically alterable read only memory semiconductor device.
  45. Yang, Jean Y.; Halliyal, Arvind; Jafarpour, Amir H.; Kamal, Tazrien; Ramsbey, Mark T.; Lingunis, Emmanuil; Shiraiwa, Hidehiko, Memory manufacturing process using bitline rapid thermal anneal.
  46. Halliyal, Arvind; Kamal, Tazrien; Ngo, Minh Van; Ramsbey, Mark T.; Shields, Jeffrey A.; Yang, Jean Y.; Lingunis, Emmanuil; Hui, Angela T.; Ogura, Jusuke, Memory wordline hard mask.
  47. Boaz Eitan IL; Ilan Bloom IL, Method and circuit for minimizing the charging effect during manufacture of semiconductor devices.
  48. Eitan, Boaz; Bloom, Ilan, Method and circuit for minimizing the charging effect during manufacture of semiconductor devices.
  49. Kim, Hyeon-Seag, Method and system for qualifying an ONO layer in a semiconductor device.
  50. Eitan Boaz,ILX ; Rotstein Israel,ILX, Method for creating diffusion areas for sources and drains without an etch step.
  51. Hong Gary (Hsinchu TWX), Method for fabricating a self aligned mask ROM.
  52. Fuh-Cheng Jong TW; Kent Kuohua Chang TW, Method for forming a nonvolatile memory with optimum bias condition.
  53. Gill Manzur (Saratoga CA) Shacham Etan (Cupertino CA), Method for forming field oxide regions.
  54. Woo Been-Jon (Saratoga CA) Holler Mark A. (Palo Alto CA), Method for improving erase characteristics of buried bit line flash EPROM devices without using sacrificial oxide growth.
  55. Chang Thomas T. L. (Santa Clara CA) Ho Chun (Cupertino CA) Malhotra Arun K. (Mt. View CA), Method for making electrically programmable memory device by doping the floating gate by implant.
  56. Reisinger Hans,DEX, Method for operating a non-volatile memory cell arrangement.
  57. Hakozaki Kenji (Tenri JPX) Sato Shin-ichi (Nara JPX), Method for producing a floating gate memory device including implanting ions through an oxidized portion of the silicon.
  58. Kazerounian Reza (Alameda CA) Eitan Boaz (Sunnyvale CA), Method for programming a floating gate memory device.
  59. Beatty Timothy S., Method for protecting a transistor gate from charge damage.
  60. Sugiyama Toshinobu (Kanagawa JPX) Sakurai Hiroshi (Kanagawa JPX), Method of determining conditions for plasma silicon nitride film growth and method of manufacturing semiconductor device.
  61. Ranaweera Jeewika Chandanie,CAX ; Kalastirsky Ivan ; Gulersen Elvira,CAX ; Ng Wai Tung,CAX ; Salama Clement Andre T.,CAX, Method of fabricating a fast programmable flash E.sup.2 PROM cell.
  62. Sakurai Yasuhiro (Saitama JPX) Kishi Toshiyuki (Saitama JPX), Method of fabricating a semiconductor nonvolatile storage device.
  63. Sun, Yu; Van Buskirk, Michael A.; Ramsbey, Mark T., Method of fabricating double densed core gates in sonos flash memory.
  64. Mehta Sunil D., Method of forming a non-volatile memory device.
  65. Hsu Chen-Chung,TWX, Method of making ROM components.
  66. Shrivastava Ritu (Fremont CA), Method of making flash EPROM cell having improved erase characteristics by using a tilt angle implant.
  67. McElroy David J. (Houston TX), Method of making high density semiconductor device such as floating gate electrically programmable ROM or the like.
  68. Ghneim Said N. ; Fulford ; Jr. H. Jim, Method of making non-volatile memory device having a floating gate with enhanced charge retention.
  69. Komori Kazuhiro (Kodaira JPX) Kuroda Kenichi (Tachikawa NY JPX) Sugiura June (Troy NY), Method of making semiconductor device with memory cells and peripheral transistors.
  70. Jacobs Erwin (Vaterstetten DEX) Schwabe Ulrich (Munich DEX) Takacs Dezso (Munich DEX), Method of making very short channel length MNOS and MOS devices by double implantation of one conductivity type subseque.
  71. Hashimoto, Hiroshi; Takahashi, Koji, Method of manufacturing a semiconductor memory device with a buried bit line.
  72. Hayabuchi Itsunari (Chiba JPX), Method of producing semiconductor devices of a MONOS type.
  73. Efraim Aloni IL; Shai Kfir IL; Menchem Vofsy IL; Avi Ben-Guigui IL, Methods for fabricating a semiconductor chip having CMOS devices and a fieldless array.
  74. Liang Mong-Song,TWX ; Kuo Di-Son,TWX ; Hsu Ching-Hsiang,TWX ; Lin Ruei-Ling,TWX, Multi-level, split-gate, flash memory cell.
  75. Wen Jemmy,TWX, Multi-stage ROM structure and method for fabricating the same.
  76. Schmitt-Landsiedel Doris,DEX ; Thewes Roland,DEX ; Bollu Michael,DEX ; von Basse Paul-Werner,DEX, Multi-value read-only memory cell having an improved signal-to-noise ratio.
  77. Boaz Eitan IL, NROM cell with generally decoupled primary and secondary injection.
  78. Eitan Boaz,ILX, NROM cell with improved programming, erasing and cycling.
  79. Boaz Eitan IL, NROM cell with self-aligned programming and erasure areas.
  80. Eitan, Boaz, NROM cell with self-aligned programming and erasure areas.
  81. Boaz Eitan,ILX, NROM fabrication method.
  82. Eitan Boaz,ILX, NROM fabrication method with a periphery portion.
  83. Schumann Steven J. (Sunnyvale CA) Hu James C. (Saratoga CA), Narrow width EEPROM with single diffusion electrode formation.
  84. Yider Wu ; Jean Yee-Mei Yang ; Mark Ramsbey ; Emmanuel H. Lingunis ; Yu Sun, Nitride barrier layer for protection of ONO structure from top oxide loss in a fabrication of SONOS flash memory.
  85. Wu, Yider; Yang, Jean Yee-Mei; Ramsbey, Mark; Lingunis, Emmanuel H.; Sun, Yu, Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory.
  86. Eitan, Boaz, Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping.
  87. Eitan, Boaz, Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping.
  88. Bass ; Jr. Roy S. (Underhill VT) Bhattacharyya Arup (Essex Junction VT) Grise Gary D. (Colchester VT), Non-volatile memory cell having Si rich silicon nitride charge trapping layer.
  89. Aozasa Hiroshi,JPX ; Hayashi Yutaka,JPX, Non-volatile memory cell having dual gate electrodes.
  90. Christie Kenneth Howard (Hopewell Junction NY) DeWitt David (Los Gatos CA) Johnson William Stanford (Hopewell Junction NY), Non-volatile metal nitride oxide semiconductor device.
  91. Mirabel Jean-Michel (Gardanne FRX), Non-volatile programmable bistable multivibrator in predefined initial state for memory redundancy circuit.
  92. Mirabel Jean-Michel (Gardanne FRX), Non-volatile programmable bistable multivibrator, programmable by the source, for memory redundancy circuit.
  93. Mitchell Allan T. (Garland TX) Riemenschneider Bert R. (Murphy TX), Non-volatile semiconductor memory.
  94. Torii, Satoshi, Non-volatile semiconductor memory and its driving method.
  95. Eitan Boaz,ILX, Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping.
  96. Ohya Shuichi (Tokyo JA) Kikuchi Masanori (Tokyo JA), Non-volatile semiconductor memory device.
  97. Tsuruta Masataka (Kyoto JPX) Shimoji Noriyuki (Kyoto JPX) Nakao Hironobu (Kyoto JPX) Ozawa Takanori (Kyoto JPX), Non-volatile semiconductor memory device and memory circuit using the same.
  98. Kohda Kenji (Hyogo JPX) Toyama Tsuyoshi (Hyogo JPX) Ando Nobuaki (Hyogo JPX) Noguchi Kenji (Hyogo JPX) Kobayashi Shinichi (Hyogo JPX), Non-volatile semiconductor memory device with facility of storing tri-level data.
  99. Bate Robert T. (Garland TX), Non-volatile semiconductor memory elements.
  100. Tsuruta Masataka (Kyoto JPX), Non-volatile semiconductor memory with outer drain diffusion layer.
  101. Eitan Boaz (Sunnyvale CA) Kazerounian Reza (Fremont CA), Nonvolatile floating gate transistor structure.
  102. Fratin Lorenzo,ITX ; Ravazzi Leonardo,ITX ; Riva Carlo,ITX, Nonvolatile memory cell and a method for forming the same.
  103. Wang Hsingya A. (Saratoga CA) Hsu James J. (Saratoga CA), Nonvolatile memory cell formed using self aligned source implant.
  104. Wang Hsingya Arthur (Saratoga CA) Hsu James Juen (Saratoga CA), Nonvolatile memory cell formed using self aligned source implant.
  105. Shimoji Noriyuki (Kyoto JPX), Nonvolatile semiconductor device having charge trap film containing silicon crystal grains.
  106. Sakui Koji,JPX ; Miyamoto Junichi,JPX, Nonvolatile semiconductor memory.
  107. Takei Akira (Yokohama JPX) Hika Yoshihiko (Yokohama JPX) Miida Takashi (Tokyo JPX), Nonvolatile semiconductor memory device.
  108. Fujiwara Ichiro,JPX ; Hayashi Yutaka,JPX, Nonvolatile semiconductor memory device and writing and erasing method of the same.
  109. Ramsbey, Mark T.; Yang, Jean Y.; Shiraiwa, Hidehiko; Van Buskirk, Michael A.; Rogers, David M.; Sunkavalli, Ravi S.; Wang, Janet S.; Derhacobian, Narbeh, Planar structure for non-volatile memory devices.
  110. You Jyh-Cheng,TWX ; Chen Pei-Hung,TWX ; Yu Shau-Tsung,TWX ; Chu Yi-Jing,TWX, Post metal code engineering for a ROM.
  111. Stephen K. Park ; George Jon Kluth ; Bharath Rangarajan, Process for creating a flash memory cell using a photoresist flow operation.
  112. Wang Hsingya A. (San Jose CA), Process for fabricating a control gate for a floating gate FET.
  113. Komori, Hideki; Foote, David K.; Wang, Fei; Rangarajan, Bharath, Process for fabricating a non-volatile memory device.
  114. Rangarajan, Bharath; Foote, David; Wang, Fei; Park, Steven K., Process for fabricating a non-volatile memory device.
  115. Park Stephen Keetai ; Thurgate Tim ; Rangarajan Bharath, Process for fabricating an MNOS flash memory device.
  116. Dawn M. Hopper ; David K. Foote ; Bharath Rangarajan, Process for fabricating an ONO structure.
  117. Holler Mark A. (Palo Alto CA) Tam Simon M. (San Mateo CA), Process for fabricating electrically alterable floating gate memory devices.
  118. Bharath Rangarajan ; David K. Foote ; Fei Wang ; Dawn M. Hopper ; Stephen K. Park ; Jack Thomas ; Mark Chang ; Mark Ramsbey, Process for fabricating high density memory cells using a polysilicon hard mask.
  119. Foote David K. ; Rangarajan Bharath ; Wang Fei ; Park Steven K., Process for forming a bit-line in a MONOS device.
  120. George Jonathan Kluth ; Stephen K. Park ; Arvind Halliyal ; David K. Foote, Process for optimizing pocket implant profile by RTA implant annealing for a non-volatile semiconductor device.
  121. Schwabe Ulrich (Vaterstetten DEX) Jacobs Erwin (Munich DEX), Process for producing an integrated multi-layer insulator memory cell.
  122. Yang Ming-Tzong (Hsin-chu TWX) Huang Cheng-Han (Hsin-chu TWX) Hsue Chen-Chiu (Hsin-chu TWX), Process for producing memory devices having narrow buried N+lines.
  123. Eitan Boaz,ILX, Process for producing two bit ROM cell utilizing angled implant.
  124. Jacobs Erwin (Vaterstetten DEX) Schwabe Ulrich (Munich DEX), Process for production of integrated MOS circuits with and without MNOS memory transistors in silicon-gate technology.
  125. Kodama Noriaki (Tokyo JPX), Process of fabricating floating gate type field effect transistor having drain region gently varied in impurity profile.
  126. Chen Teh-Yi J. (Cupertino CA), Protected programmable transistor with reduced parasitic capacitances and method of fabrication.
  127. Ghandehari, Kouros; Lingunis, Emmanuil H.; Chang, Mark S.; Hui, Angela; Bell, Scott; Ogura, Jusuke, RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist.
  128. Chang Kent Kuohua ; Chi David, RTCVD oxide and N.sub.2 O anneal for top oxide of ONO film.
  129. Uramoto Shinichi (Hyogo JPX) Matsumura Tetsuya (Hyogo JPX) Yoshimoto Masahiko (Hyogo JPX) Ishihara Kazuya (Hyogo JPX) Segawa Hiroshi (Hyogo JPX), Read only memory for storing multi-data.
  130. Kobatake Hiroyuki (Tokyo JPX), Read only semiconductor memory having multiple bit cells.
  131. Krautschneider Wolfgang,DEX ; Risch Lothar,DEX ; Hofmann Franz,DEX ; Rosner Wolfgang,DEX, Read-only-memory cell arrangement using vertical MOS transistors and gate dielectrics of different thicknesses and metho.
  132. Ikeda Shuji,JPX ; Meguro Satoshi,JPX ; Hashiba Soichiro,JPX ; Kuramoto Isamu,JPX ; Koike Atsuyoshi,JPX ; Sasaki Katsuro,JPX ; Ishibashi Koichiro,JPX ; Yamanaka Toshiaki,JPX ; Hashimoto Naotaka,JPX ; , SRAM having load transistor formed above driver transistor.
  133. Ramsbey, Mark T.; Sun, Yu; Chang, Chi, Salicided gate for virtual ground arrays.
  134. Chi-Yung Wu,TWX ; Chen Ling ; Peng Tony,TWX, Select gate enhanced high density read-only-memory device.
  135. Ma Yueh Y. (Los Altos CA) Chang Kuo-Tung (San Jose CA), Self-aligned dual-bit split gate (DSG) flash EEPROM cell.
  136. Tickle Andrew C. (Los Altos CA), Self-refreshing memory cell.
  137. Franciscus Petrus Widdershoven NL; Jurriaan Schmitz NL, Semiconductor device.
  138. Aoki Hitoshi (Nara JPX), Semiconductor device ROM having an offset region.
  139. Nakao Hironobu (Kyoto JPX), Semiconductor device including nonvolatile memories.
  140. Komori Kazuhiro (Kodaira JPX) Kuroda Kenichi (Tachikawa NY JPX) Sugiura June (Troy NY), Semiconductor device of an LDD structure having a floating gate.
  141. Lee Roger R. (Boise ID), Semiconductor floating gate device having improved channel-floating gate interaction.
  142. Takahashi, Koji, Semiconductor memory capable of being driven at low voltage and its manufacture method.
  143. Aoyama Masaharu (Yokohama JPX) Hiraki Shunichi (Yokohama JPX) Yonezawa Toshio (Yokosuka JPX), Semiconductor memory device.
  144. Van Berkel Cornelis (Brighton GB2) Bird Neil C. (Horley GB2), Semiconductor memory device.
  145. Shimoji Noriyuki (Kyoto JPX), Semiconductor memory device and method of reading out information for the same.
  146. Iwahashi Hiroshi,JPX, Semiconductor memory device capable of storing plural-bit data in a single memory cell.
  147. Odake Yoshinori (Osaka JPX) Okuda Yasushi (Osaka JPX), Semiconductor memory device having an energy gap for high speed operation.
  148. Shimoji Noriyuki (Kyoto JPX), Semiconductor memory device having an insulating film and a trap film joined in a channel region.
  149. Ichiguchi Tetsuichiro (Hyogo JPX), Semiconductor memory device having sense amplifier having improved activation timing thereof and operating method thereo.
  150. Beale Julian Robert Anthony (Salfords near Redhill EN) Daniel Peter James (Salfords near Redhill EN), Semiconductor memory elements.
  151. Fastow, Richard M.; Hollmer, Shane C.; Chen, Pau-Ling; Van Buskirk, Michael; Higashitani, Masaaki, Sidewall NROM and method of manufacture thereof for non-volatile memory cells.
  152. Ramsbey, Mark T.; Yang, Jean Y.; Shiraiwa, Hidehiko; Van Buskirk, Michael A.; Rogers, David M.; Sunkavalli, Ravi; Wang, Janet; Derhacobian, Narbeh; Wu, Yider, Simultaneous formation of charge storage and bitline to wordline isolation.
  153. Georgescu Sorin ; Mihnea Andrei ; Vanco Radu, Single transistor non-volatile electrically alterable semiconductor memory device.
  154. Jean Yee-Mei Yang ; Mark T. Ramsbey ; Emmanuil Manos Lingunis ; Yider Wu ; Tazrien Kamal ; Yi He ; Edward Hsia ; Hidehiko Shiraiwa, Source drain implant during ONO formation for improved isolation of SONOS devices.
  155. Chen Shih-Ou (Fremont CA) McCollum John L. (Saratoga CA) Chiang Steve S. (Saratoga CA), Structure for protecting thin dielectrics during processing.
  156. Su Hung-Der,TWX ; Lee Jian-Hsing,TWX ; Kuo Di-Son,TWX, Test structures for monitoring gate oxide defect densities and the plasma antenna effect.
  157. Hsu Chen-Chung,TWX, Three-dimensional, deep-trench, high-density read-only memory (ROM) and its manufacturing method.
  158. Eitan Boaz,ILX, Two bit ROM cell and process for producing same.
  159. Eitan Boaz,ILX, Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping.
  160. Janning John L. (Dayton OH), Two bit vertically/horizontally integrated memory cell.
  161. Halliyal, Arvind; Ramsbey, Mark T.; Zhang, Wei; Randolph, Mark W.; Cheung, Fred T. K., Use of high-K dielectric material in modified ONO structure for semiconductor devices.
  162. Halliyal, Arvind; Ramsbey, Mark T.; Chang, Kuo-Tung; Tripsas, Nicholas H.; Ogle, Robert B., Use of high-k dielectric materials in modified ONO structure for semiconductor devices.
  163. Tigelaar Howard L. (Allen TX) Mitchell Allan T. (Garland TX) Riemenschneider Bert R. (Murphy TX) Paterson James L. (Richardson TX), X-cell EEPROM array.

이 특허를 인용한 특허 (30)

  1. Lee, Peter Wung; Hsu, Fu-Chang, Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array.
  2. Lee, Chang-hyun, Charge trapping nonvolatile memory devices with a high-K blocking insulation layer.
  3. Lee, Peter; Hsu, Fu-Chang, Circuit and method for multiple-level programming, reading, and erasing dual-sided nonvolatile memory cell.
  4. Irani, Rustom; Eitan, Boaz; Bloom, Ilan; Shappir, Assaf, Double density NROM with nitride strips (DDNS).
  5. Sofer,Yair; Maayan,Eduardo; Betser,Yoram, Dynamic matching of signal path and reference path for sensing.
  6. Lu, Chi-Pin; Luo, Shing-Ann, Fabricating method of non-volatile memory cell.
  7. Bu, Jiankang, High-performance CMOS-compatible non-volatile memory cell and related method.
  8. Betser, Yoram; Kushnarenko, Alexander; Dadashev, Oleg, Measuring and controlling current consumption and output current of charge pumps.
  9. Polansky, Yan; Lavan, Avi, Memory array programming circuit and a method for using the circuit.
  10. Bae, Dong-II, Memory devices having volatile and non-volatile memory characteristics and methods of operating the same.
  11. Chen, Chien-Hung; Chen, Tzu-Ping; Chang, Yu-Jen, Method for manufacturing non-volatile memory.
  12. Maayan, Eduardo; Eitan, Boaz; Lann, Ameet, Method for programming a reference cell.
  13. Eitan, Boaz; Shainsky, Natalie, Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection.
  14. Shappir,Assaf; Eisen,Shai, Method, circuit and systems for erasing one or more non-volatile memory cells.
  15. Cohen, Guy; Polansky, Yan, Method, system and circuit for programming a non-volatile memory array.
  16. Heo, Jin-Hwa; Kim, Chul-Sung; Koo, Bon-Young; Hwang, Ki-Hyun; Lee, Chang-Hyun, Methods of forming non-volatile memory devices.
  17. Chen, Chien-Hung; Chen, Tzu-Ping; Chang, Yu-Jen, Non-volatile memory.
  18. Chen, Chien-Hung; Chen, Tzu-Ping; Chang, Yu-Jen, Non-volatile memory and manufacturing method thereof.
  19. Eitan,Boaz, Non-volatile memory cell and non-volatile memory devices.
  20. Lee, Chang-Hyun; Choi, Jung-Dal, Non-volatile memory devices and methods of operating the same.
  21. Wang, Xuguang; Huang, Shuiyuan; Dimitrov, Dimitar V.; Tang, Michael Xuefei; Xue, Song S., Non-volatile memory with programmable capacitance.
  22. Wang, Xuguang; Huang, Shuiyuan; Dimitrov, Dimitar V.; Tang, Michael Xuefei; Xue, Song S., Non-volatile multi-bit memory with programmable capacitance.
  23. Wang, Xuguang; Huang, Shuiyuan; Dimitrov, Dimitar V.; Tang, Michael Xuefei; Xue, Song S., Non-volatile multi-bit memory with programmable capacitance.
  24. Lee, Chang-Hyun; Choi, Jung-Dal; Ye, Byoung-Woo, Non-volatile semiconductor memory devices.
  25. Lee, Chang-Hyun; Choi, Jung-Dal; Ye, Byoung-Woo, Non-volatile semiconductor memory devices.
  26. Lee, Chang-Hyun; Choi, Jung-Dal; Ye, Byoung-Woo, Non-volatile semiconductor memory devices.
  27. Lee,Sung Hae; Lee,Chang Hyun; Hwang,Ki Hyun; Baek,Sung Kweon; Park,Kwang Min, Non-volatile semiconductor memory devices and methods of fabricating the same.
  28. Lusky,Eli; Eitan,Boaz; Cohen,Guy; Maayan,Eduardo, Operating array cells with matched reference cells.
  29. Eitan, Boaz, Secondary injection for NROM.
  30. Lusky,Eli, Threshold voltage shift in NROM cells.
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