Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/20
H01L-021/02
H01L-021/36
출원번호
US-0103681
(2005-04-12)
발명자
/ 주소
Langdo,Thomas A.
Lochtefeld,Anthony J.
출원인 / 주소
Amberwave Systems Corporation
대리인 / 주소
Goodwin Procter, LLP
인용정보
피인용 횟수 :
40인용 특허 :
220
초록▼
Methods for fabricating facetless semiconductor structures using commercially available chemical vapor deposition systems are disclosed herein. A key aspect of the invention includes selectively depositing an epitaxial layer of at least one semiconductor material on the semiconductor substrate whil
Methods for fabricating facetless semiconductor structures using commercially available chemical vapor deposition systems are disclosed herein. A key aspect of the invention includes selectively depositing an epitaxial layer of at least one semiconductor material on the semiconductor substrate while in situ doping the epitaxial layer to suppress facet formation. Suppression of faceting during selective epitaxial growth by in situ doping of the epitaxial layer at a predetermined level rather than by manipulating spacer composition and geometry alleviates the stringent requirements on the device design and increases tolerance to variability during the spacer fabrication.
대표청구항▼
The invention claimed is: 1. A method of fabricating a semiconductor structure, the method comprising: providing a semiconductor substrate having a surface including a first portion and a second portion proximal to the first portion; forming a gate stack over the first portion of said substrate, th
The invention claimed is: 1. A method of fabricating a semiconductor structure, the method comprising: providing a semiconductor substrate having a surface including a first portion and a second portion proximal to the first portion; forming a gate stack over the first portion of said substrate, the gate stack comprising a dielectric; and thereafter, selectively depositing an epitaxial layer of at least one semiconductor material on the second portion of the substrate adjacent to the gate stack while in situ doping the epitaxial layer to a first predetermined level, to thereby suppress formation of facets on the epitaxial layer, wherein an ambient pressure during selective deposition of the epitaxial layer is greater than about 5 Torr. 2. The method of claim 1, wherein the selective deposition of the epitaxial layer results in the formation of a substantially facetless semiconductor region. 3. The method of claim 1, wherein the epitaxial layer is deposited in a chemical vapor deposition system. 4. The method of claim 3, wherein the chemical vapor deposition system is selected from the group consisting of a reduced-pressure chemical vapor deposition system, an atmospheric-pressure chemical vapor deposition system, and a plasma-enhanced chemical vapor deposition system. 5. The method of claim 3, wherein the chemical vapor deposition system comprises a single-wafer system. 6. The method of claim 1, wherein the step of selectively depositing an epitaxial layer comprises use of a source gas. 7. The method of claim 6, wherein the source gas comprises at least one precursor gas and a carrier gas. 8. The method of claim 7, wherein the carrier gas comprises hydrogen. 9. The method of claim 7, wherein the at least one precursor gas comprises a silicon precursor gas. 10. The method of claim 9, wherein the silicon precursor gas is selected from the group consisting of silane, disilane, trisilane, and dichlorosilane. 11. The method of claim 7, wherein the at least one precursor gas comprises a germanium precursor gas. 12. The method of claim 11, wherein the germanium precursor gas is selected from the group consisting of germane, digermane, germanium tetrachloride, or germanium dichloride. 13. The method of claim 7, wherein the source gas further comprises an etchant for suppressing nucleation of the at least one semiconductor material over the dielectric during deposition. 14. The method of claim 13, wherein the etchant comprises at least one of hydrogen chloride and chlorine. 15. The method of claim 13, wherein the at least one precursor gas comprises dichlorosilane and germane, the carrier gas comprises hydrogen, the etchant comprises hydrogen chloride, and the epitaxial layer comprises Si1-xGex. 16. The method of claim 15, wherein x≈0.2. 17. The method of claim 15, wherein the ambient pressure is less than approximately 20 Torr. 18. The method of claim 15, wherein the ambient temperature during the selective deposition of the epitaxial layer is selected from a range of 500째 C. to about 900째 C. 19. The method of claim 18, wherein the temperature is approximately 750째 C. 20. The method of claim 18, wherein the temperature is approximately 700째 C. 21. The method of claim 1, wherein the epitaxial layer is doped by adding a dopant to the epitaxial layer during deposition of the epitaxial layer, the dopant selected from the group consisting of phosphorus, arsenic, antimony, and boron. 22. The method of claim 21, wherein adding the dopant to the epitaxial layer comprises the use of a dopant gas selected from the group consisting of phosphine, arsine, stibine, and diborane. 23. The method of claim 21, wherein the dopant comprises boron. 24. The method of claim 1, wherein the first predetermined level of doping is greater than about 1017. 25. The method of claim 1, wherein the epitaxial layer comprises at least one of silicon and germanium. 26. The method of claim 25, wherein the epitaxial layer comprises germanium. 27. The method of claim 25, wherein the epitaxial layer extends to a height above the substrate ranging from about 10 nm to about 100 nm. 28. The method of claim 1, wherein the dielectric comprises at least one of silicon dioxide and silicon nitride. 29. The method of claim 28, wherein the dielectric comprises a two-layered spacer structure comprising a silicon oxide liner and a silicon nitride spacer disposed thereon. 30. The method of claim 29, wherein a thickness of the silicon oxide liner is about 25 nm. 31. The method of claim 29, wherein a thickness of the silicon nitride spacer ranges from about 30 nm to about 100 nm. 32. The method of claim 29, wherein the silicon oxide liner undercuts the silicon nitride spacer such that the silicon nitride spacer extends further laterally from the gate stack than the silicon oxide liner. 33. The method of claim 1, wherein the semiconductor substrate comprises silicon. 34. The method of claim 1, wherein the semiconductor substrate comprises a silicon wafer; an insulating layer disposed thereon; and a strained semiconductor layer disposed above the insulating layer. 35. The method of claim 34, wherein the strained semiconductor layer comprises at least one of silicon or germanium. 36. The method of claim 1, wherein the semiconductor substrate comprises an insulating layer. 37. The method of claim 1, wherein the epitaxial layer is deposited at a rate greater than about 1 nm/mm. 38. The method of claim 1, wherein a strained semiconductor material is disposed beneath the gate stack. 39. The method of claim 38, wherein the strained semiconductor material comprises silicon. 40. The method of claim 1, further comprising forming a contact material above the epitaxial layer. 41. The method of claim 40, wherein the contact material comprises a material selected from the group consisting of cobalt, titanium, tungsten, molybdenum, platinum, nickel, and tantalum. 42. The method of claim 41, wherein the contact material comprises nickel. 43. The method of claim 41, wherein the contact material comprises tungsten. 44. The method of claim 1, wherein the surface of the semiconductor substrate has a substantially (100) crystallographic orientation. 45. The method of claim 1, wherein the dielectric comprises a sidewall having an angle relative to the semiconductor substrate, the angle selected from a range of about 60째 to about 90째. 46. The method of claim 45, wherein the semiconductor substrate has a <110> crystallographic plane, the sidewall being substantially aligned therewith. 47. The method of claim 45, wherein the semiconductor substrate has a <100> crystallographic plane, the sidewall being substantially aligned therewith. 48. The method of claim 1, wherein the epitaxial layer is deposited adjacent to an isolation region. 49. The method of claim 48, wherein the isolation region comprises silicon oxide. 50. The method of claim 48, wherein the isolation region comprises a shallow trench. 51. The method of claim 4, wherein the chemical vapor deposition system is a single-wafer reduced-pressure chemical vapor deposition system. 52. The method of claim 8, wherein the carrier gas consists essentially of hydrogen. 53. The method of claim 15, wherein the epitaxial layer is doped by adding a dopant comprising boron to the epitaxial layer during deposition of the epitaxial layer. 54. The method of claim 53, wherein x≈0.2. 55. The method of claim 53, further comprising forming a contact material above the epitaxial layer, wherein the contact material comprises at least one material selected from the group consisting of nickel and tungsten. 56. The method of claim 15, wherein the dielectric comprises a two-layered spacer structure including a silicon oxide liner and a silicon nitride spacer disposed thereon. 57. The method of claim 56, wherein the silicon oxide liner undercuts the silicon nitride spacer such that the silicon nitride spacer extends further laterally from the gate stack than does the silicon oxide liner. 58. The method of claim 56, wherein a strained semiconductor material is disposed beneath the gate stack. 59. The method of claim 58, wherein the strained semiconductor material consists essentially of silicon. 60. The method of claim 56, further comprising forming a contact material above the epitaxial layer, wherein the contact material comprises at least one material selected from the group consisting of nickel and tungsten. 61. The method of claim 25, wherein the epitaxial layer comprises silicon and germanium. 62. The method of claim 39, wherein the strained semiconductor material consists essentially of silicon. 63. The method of claim 62, further comprising forming a contact material above the epitaxial layer, wherein the contact material comprises at least one material selected from the group consisting of nickel and tungsten.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (220)
Lung Hsing Lan,TWX ; Lu Tao Cheng,TWX ; Wang Mam Tsung,TWX, 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate.
Fischer Hermann,DEX ; Hofmann Franz,DEX, CMOS integrated circuit including forming doped wells, a layer of intrinsic silicon, a stressed silicon germanium layer where germanium is between 25 and 50%, and another intrinsic silicon layer.
Harame David L. (Mohegan Lake NY) Patton Gary L. (Poughkeepsie NY) Stork Maria C. (Yorktown Heights NY), Complementary bipolar transistor structure and method for manufacture.
Baca Albert G. (Albuquerque NM) Drummond Timothy J. (Albuquerque NM) Robertson Perry J. (Albuquerque NM) Zipperian Thomas E. (Albuquerque NM), Complementary junction heterostructure field-effect transistor.
Ismail Khaled E. (Cairo NY EGX) Stern Frank (Pleasantville NY), Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers.
Horstmann Manfred,DEX ; Wieczorek Karsten,DEX ; Hause Frederick N., Device improvement by source to drain resistance lowering through undersilicidation.
Harari Eliyahou ; Guterman Daniel C. ; Samachisa George ; Yuan Jack H., Dual floating gate EEPROM cell array with steering gates shared adjacent cells.
Dennard Robert H. (Peekskill NY) Meyerson Bernard S. (Yorktown Heights NY) Rosenberg Robert (Peekskill NY), Fabrication of defect free silicon on an insulating substrate.
Wieczorek, Karsten; Stephan, Rolf; Horstmann, Manfred; Kruegel, Stephan, Field effect transistor with an improved gate contact and method of fabricating the same.
Furukawa Toshiharu ; Ellis-Monaghan John Joseph ; Slinkman James Albert, High resolution dopant/impurity incorporation in semiconductors via a scanned atomic force probe.
Jack Oon Chu ; Richard Hammond ; Khalid EzzEldin Ismail ; Steven John Koester ; Patricia May Mooney ; John A. Ott, High speed composite p-channel Si/SiGe heterostructure for field effect devices.
Brigham Lawrence N. (Beaverton OR) Lee Yung-Huei (Sunnyvale CA) Chau Robert S. (Beaverton OR) Cotner Raymond E. (Beaverton OR), High tensile nitride layer.
Meyerson Bernard S. (Yorktown Heights NY), Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers.
Bich-Yen Nguyen ; William J. Taylor, Jr. ; Philip J. Tobin ; David L. O'Meara ; Percy V. Gilbert ; Yeong-Jyh T. Lii ; Victor S. Wang, Method for forming a semiconductor device with an opening in a dielectric layer.
Brasen Daniel (Lake Hiawatha NJ) Fitzgerald ; Jr. Eugene A. (Bridgewater NJ) Green Martin L. (New Providence NJ) Xie Ya-Hong (Flemington NJ), Method for making low defect density semiconductor heterostructure and devices made thereby.
Selvakumar Chettypalayam R. (Waterloo CAX) Chamberlain Savvas G. (Waterloo CAX), Method for making silicon-germanium devices using germanium implantation.
Andideh Ebrahim ; Brigham Lawrence ; Chau Robert S. ; Ghani Tahir ; Jan Chia-Hong ; Sandford Justin ; Taylor Mitchell C., Method of fabricating a MOS transistor with a raised source/drain extension.
Shideler, Jay Albert; Prasad, Jayasimha Swamy; Schlupp, Ronald Lloyd; Bechdolt, Robert William, Method of fabricating a bipolar transistor using selective epitaxially grown SiGe base layer.
Fitzgerald, Eugene A., Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits.
Dennard Robert H. (Peekskill NY) Meyerson Bernard S. (Yorktown Heights NY) Rosenberg Robert (Peekskill NY), Method of fabricating defect-free silicon on an insulating substrate.
Lynch William T. (Apex NC) Wang Kang L. (Santa Monica CA) Tanner Martin O. (Duarte CA), Method of fabricating quantum bridges by selective etching of superlattice structures.
Bin Yu ; William G. En ; Judy Xilin An ; Concetta E. Riccobene, Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer.
Abernathey John R. (Essex VT) Cronin John E. (Milton VT) Lasky Jerome B. (Essex Junction VT), Method of forming metal-strapped polysilicon gate electrode for FET device.
Gardner Mark I. ; Fulford H. Jim ; Wristers Derick J., Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication.
Cronin John E. (Milton VT) Kaanta Carter W. (Colchester VT) Mann Randy W. (Jericho VT) Meulemans Darrell (Jericho VT) Starkey Gordon S. (Essex Junction VT), Method of making overpass mask/insulator for local interconnects.
Godbey David J. (Bethesda MD) Hughes Harold L. (West River MD) Kub Francis J. (Severna Park MD), Method of producing a thin silicon-on-insulator layer.
Taylor, Jr., William J.; Orlowski, Marius; Gilmer, David C.; Alluri, Prasad V.; Hobbs, Christopher C.; Rendon, Michael J.; Clejan, Iuval R., Method of recrystallizing an amorphous region of a semiconductor.
Dmbkes Heinrich (Ulm DEX) Herzog Hans-J. (Neu-Ulm DEX) Jorke Helmut (Gerstetten DEX), Modulation doped field effect transistor with doped SixGe1-x-intrinsic Si layering.
Maa, Jer-Shen; Tweet, Douglas J.; Hsu, Sheng Teng; Lee, Jong-Jan, Molecular hydrogen implantation method for forming a relaxed silicon germanium layer with high germanium content.
Arimilli, Ravi Kumar; Fields, Jr., James Stephen; Guthrie, Guy Lynn; Joyner, Jody Bern; Lewis, Jerry Don, Multiprocessor system bus protocol with group addresses, responses, and priorities.
Canaperi, Donald F.; Chu, Jack Oon; D'Emic, Christopher P.; Huang, Lijuan; Ott, John Albrecht; Wong, Hon-Sum Philip, Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique.
Hartswick Thomas J. (Underhill VT) Kaanta Carter W. (Colchester VT) Lee Pei-Ing P. (Williston VT) Wright Terrance M. (Williston VT), Process for forming refractory metal silicide layers of different thicknesses in an integrated circuit.
Bensahel Daniel,FRX ; Campidelli Yves,FRX ; Hernandez Caroline,FRX ; Rivoire Maurice,FRX, Process for obtaining a layer of single-crystal germanium or silicon on a substrate of single-crystal silicon or germanium, respectively.
Ek Bruce A. ; Iyer Subramanian Srikanteswara ; Pitner Philip Michael ; Powell Adrian R. ; Tejwani Manu Jamndas, Production of substrate for tensilely strained semiconductor.
Christiansen, Silke H.; Chu, Jack O.; Grill, Alfred; Mooney, Patricia M., Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing.
Shimizu Hitoshi (Yokohama JPX) Hirayama Yoshiyuki (Yokohama JPX) Irikawa Michinori (Yokohama JPX), Schottky junction device having a Schottky junction of a semiconductor and a metal.
Kamins Theodore I. (Palo Alto) Noble David B. (Sunnyvale) Hoyt Judy L. (Palo Alto) Gibbons James F. (Palo Alto) Scott Martin P. (San Francisco CA), Selective and non-selective deposition of Si1-xGex on a Si subsrate that is partially maske.
Ozturk Mehmet C. (Cary NC) Grider Douglas T. (Pleasanton CA) Sanganeria Mahesh K. (Raleigh NC) Ashburn Stanton P. (Cary NC) Wortman Jimmie J. (Chapel Hill NC), Selective deposition of doped silicon-germanium alloy on semiconductor substrate, and resulting structures.
Ozturk Mehmet C. (Cary NC) Grider Douglas T. (Raleigh NC) Sanganeria Mahesh K. (Raleigh NC) Ashburn Stanton P. (Cary NC), Selective deposition of doped silion-germanium alloy on semiconductor substrate.
Ozturk Mehmet (Cary NC) Wortman Jimmie (Chapel Hill NC) Grider Douglas (Raleigh NC), Selective germanium deposition on silicon and resulting structures.
Ajmera, Atul Champaklal; Cabral, Jr., Cyril; Carruthers, Roy Arthur; Chan, Kevin Kok; Cohen, Guy Moshe; Kozlowski, Paul Michael; Lavoie, Christian; Newbury, Joseph Scott; Roy, Ronnen Andrew, Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby.
Cabral, Jr., Cyril; Chan, Kevin Kok; Cohen, Guy Moshe; Guarini, Kathryn Wilder; Lavoie, Christian; Roy, Ronnen Andrew; Solomon, Paul Michael, Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby.
Agnello, Paul D.; Chen, Bomy A.; Crowder, Scott W.; Divakaruni, Ramachandra; Iyer, Subramanian S.; Sinitsky, Dennis, Semiconductor chip having both compact memory and high performance logic.
Karl Brunner DE; Karl Eberl DE, Semiconductor components, in particular photodetectors, light emitting diodes, optical modulators and waveguides with multilayer structures grown on silicon substrates.
Wieczorek Karsten,DEX ; Raab Michael,DEX ; Stephan Rolf,DEX, Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same.
Brasen Daniel (Lake Hiawatha NJ) Fitzgerald ; Jr. Eugene A. (Bridgewater NJ) Green Martin L. (New Providence NJ) Monroe Donald P. (Berkeley Heights NJ) Silverman Paul J. (Millburn NJ) Xie Ya-Hong (Fl, Semiconductor heterostructure devices with strained semiconductor layers.
Kauffmann Bruce A. (Jericho VT) Lam Chung H. (Williston VT) Lasky Jerome B. (Essex Junction VT), Semiconductor memory cell and memory array with inversion layer.
Burghartz Joachim N. (Shrub Oak NY) Meyerson Bernard S. (Yorktown Heights NY) Sun Yuan-Chen (Katonah NY), SiGe thin film or SOI MOSFET and method for making the same.
Ek Bruce A. (Pelham Manor NY) Iyer Subramanian S. (Yorktown Heights NY) Pitner Philip M. (Wappingers Falls NY) Powell Adrian R. (New Milford CT) Tejwani Manu J. (Yorktown Heights NY), Substrate for tensilely strained semiconductor.
Ramaswami Ravi ; Joseph Victor ; Cao Min ; Kamins Theodore I. ; Whitlock John P. ; Prem Anil, Thermal inkjet printhead and high-efficiency polycrystalline silicon resistor system for use therein.
Chau Robert S. ; Chern Chan-Hong ; Jan Chia-Hong ; Weldon Kevin R. ; Packan Paul A. ; Yau Leopoldo D., Transistor with ultra shallow tip and method of fabrication.
Chau Robert S. ; Chern Chan-Hong ; Jan Chia-Hong ; Weldon Kevin R. ; Packan Paul A. ; Yau Leopoldo D., Transistor with ultra shallow tip and method of fabrication.
Favors ; Jr. Wesley ; MacDonald Eric William ; Mukherjee Subir ; Warriner Lynn Albert, Voltage controlled oscillator utilizing threshold voltage control of silicon on insulator MOSFETS.
Abou-Khalil, Michel J.; Gauthier, Jr., Robert J.; Lee, Tom C.; Li, Junjun; Putnam, Christopher S.; Mitra, Souvick, Design structures for high-voltage integrated circuits.
Abadeer, Wagdi W.; Chatty, Kiran V.; Gauthier, Jr., Robert J.; Rankin, Jed H.; Shi, Yun; Tonti, William R., Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures.
Abadeer, Wagdi W.; Chatty, Kiran V.; Gauthier, Jr., Robert J.; Rankin, Jed H.; Shi, Yun; Tonti, William R., Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures.
Ouyang,Qiqing C.; Chen,Xiangdong, Method for producing field effect device that includes epitaxially growing SiGe source/drain regions laterally from a silicon body.
Lochtefeld, Anthony J.; Langdo, Thomas A.; Hammond, Richard; Currie, Matthew T.; Fitzgerald, Eugene A., Methods for forming semiconductor device structures.
Kim, Young Pil; Parekh, Kunal R., Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates.
Gonzalez, Fernando, Methods of forming lines of capacitorless one transistor DRAM cells, methods of patterning substrates, and methods of forming two conductive lines.
Kim, Jin-bum; Choi, Si-young; Lee, Hyung-ik; Kim, Ki-hong; Kyoung, Yong-koo, Methods of manufacturing semiconductor devices with Si and SiGe epitaxial layers.
Tang, Sanh D.; Haller, Gordon A.; Brown, Kris K.; Allen, III, Tuman Earl, Semiconductor constructions and transistors, and methods of forming semiconductor constructions and transistors.
Abou-Khalil, Michel J.; Gauthier, Jr., Robert J.; Lee, Tom C.; Li, Junjun; Putnam, Christopher S.; Souvick, Mitra, Semiconductor-on-insulator high-voltage device structures, methods of fabricating such device structures, and design structures for high-voltage circuits.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.