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In some embodiments, a first comparator compares a first error rate and a first threshold value and a second comparator compares a second error rate and a second threshold value. Other embodiments are described and claimed.

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What is claimed is: 1. An apparatus comprising: a first comparator to compare a first error rate and a first threshold value; and a second comparator to compare a second error rate and a second threshold value; wherein the first error rate and the second error rate are error rates of a component in

What is claimed is: 1. An apparatus comprising: a first comparator to compare a first error rate and a first threshold value; and a second comparator to compare a second error rate and a second threshold value; wherein the first error rate and the second error rate are error rates of a component in a computer system. 2. The apparatus as claimed in claim 1, wherein the first error rate is a difference between an error signal and a first clock signal and the second error rate is a difference between an output of the first comparator and a second clock signal. 3. The apparatus as claimed in claim 1, wherein the first error rate is a difference between an error signal and a first clock signal and the second error rate is a difference between the error signal and a second clock signal. 4. The apparatus as claimed in claim 1, wherein an output of the first comparator is a request for preventive maintenance and an output of the second comparator identifies an imminent failure. 5. The apparatus as claimed in claim 1, further comprising a counter to count a difference between an error signal and a first clock frequency to obtain the first error rate. 6. The apparatus as claimed in claim 5, further comprising a counter to count a difference between an output of the first comparator and a second clock frequency to obtain the second error rate. 7. The apparatus as claimed in claim 1, wherein the component is at least one of a processor, a bus, a switch, a chip set, a memory, a memory module, a memory controller, a memory channel, an interconnect, an I/O controller, an I/O channel, an I/O device and a subsystem. 8. The apparatus as claimed in claim 1, wherein the first error rate is a difference between a number of errors and a frequency of a clock signal. 9. The apparatus as claimed in claim 1, further comprising a counter to count the first error rate, an up input of the counter coupled to an error signal and a down input of the counter coupled to a clock signal. 10. The apparatus as claimed in claim 1, wherein the second error rate is a difference between a number of occurrences of an output of the first comparator and a frequency of a clock signal. 11. The apparatus as claimed in claim 1, further comprising a counter to count the second error rate, an up input of the counter coupled to an output of the first comparator and a down input of the counter coupled to a clock signal. 12. The apparatus as claimed in claim 1, further comprising a counter to count the second error rate, an up input of the counter coupled to an error signal and a down input of the counter coupled to a clock signal. 13. The apparatus as claimed in claim 1, wherein the first error rate is a difference between a number of errors and a frequency of a first clock signal and the second error rate is a difference between a number of occurrences of an output of the first comparator and a frequency of a second clock signal. 14. The apparatus as claimed in claim 1, further comprising: a first counter to count the first error rate, an up input of the first counter coupled to an error signal and a down input of the first counter coupled to a first clock signal; and a second counter to count the second error rate, an up input of the second counter coupled to an output of the first comparator and a down input of the second counter coupled to a second clock signal. 15. The apparatus as claimed in claim 1, further comprising: a first interrupt signal coupled to an output of the first comparator; and a second interrupt signal coupled to an output of the second comparator. 16. The apparatus as claimed in claim 15, wherein the first interrupt signal is to request preventive maintenance and the second interrupt signal is to signal an imminent failure. 17. The apparatus as claimed in claim 1, further comprising: a first memory to store a first time stamp in response to an error signal; and a second memory to store a second time stamp in response to the output of the first comparator. 18. The apparatus as claimed in claim 17, wherein the first memory is to store a set of time stamps and the second memory is to store a set of time stamps. 19. A computer system comprising: a component; and a first comparator to compare a first error rate of the component and a first threshold value; and a second comparator to compare a second error rate of the component and a second threshold value. 20. The system as claimed in claim 19, wherein the first error rate is a difference between an error signal and a first clock signal and the second error rate is a difference between an output of the first comparator and a second clock signal. 21. The system as claimed in claim 19, wherein the first error rate is a difference between an error signal and a first clock signal and the second error rate is a difference between the first error rate and a second clock signal. 22. The system as claimed in claim 19, wherein an output of the first comparator is a request for preventive maintenance of the component and an output of the second comparator identifies an imminent failure of the component. 23. The system as claimed in claim 19, further comprising a counter to count a difference between an error signal from the component and a first clock frequency to obtain the first error rate. 24. The system as claimed in claim 19, further comprising a counter to count a difference between the first signal and a second clock frequency to obtain the second error rate. 25. The system as claimed in claim 19, wherein the component is at least one of a processor, a switch, a chip set, a bus, a memory, a memory module, a memory controller, a memory channel, an interconnect, an I/O controller, an I/O channel, an I/O device and a subsystem. 26. A method comprising: providing a first signal in response to a relationship between a first error rate and a first threshold value; and providing a second signal in response to a second error rate and a second threshold value; wherein the first error rate and the second error rate are error rates of a component in a computer system. 27. The method as claimed in claim 26, wherein the first signal is provided when the first error rate is greater than or equal to the first threshold value and the second signal is provided when the second error rate is greater than or equal to the second threshold value. 28. The method as claimed in claim 26, wherein the first error rate is a difference between an error signal and a first clock signal and the second error rate is a difference between the first signal and a second clock signal. 29. The method as claimed in claim 26, wherein the first error rate is a difference between an error signal and a first clock signal and the second error rate is a difference between the error signal and a second clock signal. 30. The method as claimed in claim 26, wherein the first signal is a request for preventive maintenance and the second signal identifies an imminent failure. 31. The method as claimed in claim 26, further comprising counting a difference between an error signal and a first clock frequency to obtain the first error rate. 32. The method as claimed in claim 31, further comprising counting a difference between the first signal and a second clock frequency to obtain the second error rate. 33. The method as claimed in claim 26, wherein the component is at least one of a processor, a bus, a switch, a chip set, a memory, a memory module, a memory controller, a memory channel, an interconnect, an I/O controller, an I/O channel, an I/O device and a subsystem. 34. An article comprising: a computer readable medium having instructions thereon which when executed cause a computer to: provide a first signal in response to a relationship between a first error rate and a first threshold value; and provide a second signal in response to a relationship between a second error rate and a second threshold value; wherein the first error rate and the second error rate are error rates of a component in a computer system. 35. The article as claimed in claim 34, wherein the first signal is provided when the first error rate is greater than or equal to the threshold value and the second signal is provided when the second error rate is greater than or equal to the second threshold value. 36. The article as claimed in claim 34, wherein the first error rate is a difference between an error signal and a first clock signal and the second error rate is a difference between the first signal and a second clock signal. 37. The article as claimed in claim 34, wherein the first error rate is a difference between an error signal and a first clock signal and the second error rate is a difference between the error signal and a second clock signal. 38. The article as claimed in claim 34, wherein the first signal is a request for preventive maintenance and the second signal identifies an imminent failure. 39. The article as claimed in claim 34, the computer readable medium further having instructions thereon which when executed cause a computer to count a difference between an error signal and a first clock frequency to obtain the first error rate. 40. The article as claimed in claim 39, the computer readable medium having further instructions thereon which when executed cause a computer to count a difference between the first signal and a second clock frequency to obtain the second error rate. 41. The article as claimed in claim 34, wherein the component is at least one of a processor, a bus, a switch, a chip set, a memory, a memory module, a memory controller, a memory channel, an interconnect, an I/O controller, an I/O channel, an I/O device and a subsystem.