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Printed wiring board and production method for printed wiring board 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/02
출원번호 US-0432640 (2002-09-30)
우선권정보 JP-2001-299668(2001-09-28); JP-2001-299669(2001-09-28); JP-2001-299670(2001-09-28)
국제출원번호 PCT/JP02/010144 (2002-09-30)
§371/§102 date 20030610 (20030610)
국제공개번호 WO03/030600 (2003-04-10)
발명자 / 주소
  • Nakai,Toru
출원인 / 주소
  • IBIDEN Co., Ltd.
대리인 / 주소
    Oblon, Spivak, McClelland, Maier &
인용정보 피인용 횟수 : 40  인용 특허 : 6

초록

A printed wiring board including solder pads excellent in frequency characteristic is provided. To do so, each solder pad 73 is formed by providing a single tin layer 74 on a conductor circuit 158 or a via 160. Therefore, a signal propagation rate can be increased, as compared with a printed wiring

대표청구항

The invention claimed is: 1. A printed wiring board manufacturing method for providing a single noble metal layer on a conductor circuit of a printed wiring board, said conductor circuit comprising copper and being exposed through an opening of an organic resin insulating layer to form a solder pad

이 특허에 인용된 특허 (6)

  1. Noda Kouta,JPX ; Inoue Tooru,JPX ; Yuan Benzhen,JPX, High density multi-layered printed wiring board, multi-chip carrier and semiconductor package.
  2. Ballard Gerald L. ; Edwards Robert D. ; Gaudiello John G. ; Markovich Voya R., Method for electroless gold deposition in the presence of a palladium seeder and article produced thereby.
  3. Lee, David M.; Francomacaro, Arthur S.; Lehtonen, Seppo J.; Charles, Jr., Harry K., Method for electroless gold plating of conductive traces on printed circuit boards.
  4. Melton Cynthia M. (Bolingbrook IL) Skipor Andrew (Glendale Heights IL), Method for forming tin-indium or tin-bismuth solder connection having increased melting temperature.
  5. Lee, Jin Yuan; Lei, Ming Ta; Huang, Ching-Cheng; Lin, Chuen-Jye, Method of making a low fabrication cost, high performance, high reliability chip scale package.
  6. Wessling Bernhard,DEX, Process for the production of metallized materials.

이 특허를 인용한 특허 (40)

  1. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Backside warpage control structure and fabrication method.
  2. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode.
  3. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode semiconductor device.
  4. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode semiconductor device.
  5. Berry, Christopher John; Huemoeller, Ronald Patrick; Hiner, David Jon, Direct-write wafer level chip scale package.
  6. Berry, Christopher John; Huemoeller, Ronald Patrick; Hiner, David Jon, Direct-write wafer level chip scale package.
  7. Berry, Christopher John; Huemoeller, Ronald Patrick; Hiner, David Jon, Direct-write wafer level chip scale package.
  8. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Electronic component package comprising fan-out and fan-in traces.
  9. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Embedded component package and fabrication method.
  10. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Embedded component package and fabrication method.
  11. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David J., Embedded electronic component package.
  12. Huemoeller, Ronald P.; Rusli, Sukianto; Hiner, David Jon, Embedded electronic component package fabrication method.
  13. Scanlan, Christopher M.; St. Amand, Roger D.; Kim, Jae Dong, Fan out build up substrate stackable package and method.
  14. Fuentes, Ruben; Dunlap, Brett, Integrated passive device structure and method.
  15. Ishido, Kiminori, Interconnect substrate, method of manufacturing interconnect substrate and semiconductor device.
  16. Kawai, Satoru; Sakai, Kenji; Chen, Liyi, Method for manufacturing a printed wiring board.
  17. Saitoh, Hirokazu; Yoshida, Ichiro, Method for manufacturing multilayer substrate for having BGA-type component thereon.
  18. Dunlap, Brett Arnold, Method of forming a plurality of electronic component packages.
  19. Kawai, Satoru; Sakai, Kenji; Chen, Liyi, Printed wiring board and method for manufacturing printed wiring board.
  20. Kim, Sang Won; Jung, Boo Yang; Kim, Sung Kyu; Yoo, Min; Lee, Seung Jae, Semiconductor device and fabricating method thereof.
  21. Do, Won Chul; Jung, Yeon Seung; Ko, Yong Jae, Semiconductor device and manufacturing method thereof.
  22. Do, Won Chul; Ko, Yong Jae, Semiconductor device comprising a conductive pad on a protruding-through electrode.
  23. Do, Won Chul; Jung, Yeon Seung; Ko, Yong Jae, Semiconductor device having through electrodes protruding from dielectric layer.
  24. Dunlap, Brett Arnold; Copia, Alexander William, Thin stackable package and method.
  25. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
  26. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
  27. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
  28. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
  29. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
  30. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
  31. Huemoeller, Ronald Patrick; Lie, Russ; Hiner, David, Two-sided fan-out wafer escape package.
  32. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  33. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  34. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  35. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  36. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  37. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  38. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  39. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  40. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package fabrication method.
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