Methods and apparatuses for a dual-polarity non-volatile memory cell
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G11C-011/24
G11C-011/21
출원번호
US-0313199
(2002-12-06)
발명자
/ 주소
Raszka,Jaroslav
출원인 / 주소
Virage Logic Corporation
대리인 / 주소
Blakely, Sokoloff, Taylor &
인용정보
피인용 횟수 :
7인용 특허 :
53
초록▼
Various apparatuses and methods in which a dual-polarity non-volatile memory cell includes a sense mode component and a charge mode component. The sense mode component communicates information stored in the dual-polarity non-volatile memory cell during a read operation. The charge mode component fa
Various apparatuses and methods in which a dual-polarity non-volatile memory cell includes a sense mode component and a charge mode component. The sense mode component communicates information stored in the dual-polarity non-volatile memory cell during a read operation. The charge mode component facilitates storing of the information stored in the dual-polarity non-volatile memory cell. The charge mode component includes a first coupling capacitor and a second tunneling capacitor in a first well, and a first tunneling capacitor and a second coupling capacitor in a second well.
대표청구항▼
I claim: 1. An integrated circuit, comprising: one or more dual-polarity non-volatile memory cells, wherein a first dual-polarity non-volatile memory cell includes: a first coupling capacitor having a first plate; a first tunneling capacitor having a second plate; a first read transistor connected
I claim: 1. An integrated circuit, comprising: one or more dual-polarity non-volatile memory cells, wherein a first dual-polarity non-volatile memory cell includes: a first coupling capacitor having a first plate; a first tunneling capacitor having a second plate; a first read transistor connected to the first coupling capacitor and the first tunneling capacitor; a second coupling capacitor having a third plate, wherein the third plate of the second coupling capacitor is electrically connected to the second plate of the first tunneling capacitor; and a second tunneling capacitor having a fourth plate, wherein the fourth plate of the second tunneling capacitor is electrically connected to a first plate of the first coupling capacitor. 2. The integrated circuit of claim 1, wherein the first dual polarity non-volatile memory cell further includes a second read transistor connected to the second coupling capacitor and the second tunneling capacitor. 3. The integrated circuit of claim 2, wherein the first read transistor has a first gate and the second read transistor has a second gate; a first floating gate encompasses the first gate, the first plate, and the second plate, the first floating gate fabricated from a single layer of polysilicon; and a second floating gate that encompasses the second gate, the third plate, and the fourth plate, the second floating gate is also fabricated from a single layer of polysilicon. 4. The integrated circuit of claim 1, wherein the first tunneling capacitor and the second tunneling capacitor are operable to store information in the dual-polarity non-volatile memory cell. 5. The integrated circuit of claim 1, wherein the second coupling capacitor stores a charge opposite in polarity to the charge stored in the first coupling capacitor. 6. The integrated circuit of claim 1, wherein the integrated circuit is fabricated using a substantially standard Complementary Metal Oxide Semiconductor (CMOS) logic process. 7. The integrated circuit of claim 2, wherein the first read transistor and the second read transistors are used to differentially communicate information stored in the dual-polarity non-volatile memory cell during a read operation. 8. The integrated circuit of claim 1, wherein the first coupling capacitor and the second coupling capacitor are comprised of a N+ doped region and a P+ doped region. 9. The integrated circuit of claim 2, further comprising: a sense amplifier, wherein the first read transistor is connected to a first input of the sense amplifier and the second transistor is connected to a second input of the sense amplifier. 10. The integrated circuit of claim 9, wherein a maximum sensing error voltage of the sense amplifier is designed to be at least smaller than a voltage margin available between a floating gate of the first coupling capacitor and a floating gate of the second coupling capacitor after a predetermined retention period. 11. The integrated circuit of claim 1, further comprising: a sense amplifier operable to provide a valid read of the information stored in the non-volatile memory cell under conditions where one of the coupling capacitors is significantly more leaky than the other coupling capacitor. 12. The integrated circuit of claim 9, wherein the sense amplifier further includes control circuitry to sense the non-volatile memory cell in differential sensing mode as well as in single mode. 13. The integrated circuit of claim 12, wherein the differential mode comprises the sense amplifier sensing a difference between a first signal value read from the first read transistor and a second signal value read from the second read transistor. 14. The integrated circuit of claim 12, wherein the single mode comprises the sense amplifier sensing a value of a voltage signal on a drain of the first read transistor relative to a circuit common. 15. The integrated circuit of claim 1, further comprising: a sense amplifier connected to the first read transistor; and a circuit to substantially eliminate current drain by the sense amplifier by switching off a current source in the sense amplifier and by reducing a voltage potential across critical nodes of the sense amplifier to substantially zero. 16. The integrated circuit of claim 1, further comprising: a sense amplifier connected to the first read transistor; and a circuit to effectively disable a current source of the sense amplifier. 17. The integrated circuit of claim 12, further comprising a circuit to effectively bring a second voltage level to critical nodes of the sense amplifier during a store operation. 18. The integrated circuit of claim 17, wherein the second voltage level is approximately Vdd. 19. The integrated circuit of claim 1, further comprising a sense amplifier to provide a valid read of the information stored in the non-volatile memory cell even if a failure occurs in either the first coupling capacitor or the second coupling capacitor but not a failure of both coupling capacitors. 20. The integrated circuit of claim 1, further comprising a sense amplifier to provide a valid read of the information stored in the non-volatile memory cell even if a failure occurs in either the first tunneling capacitor or the second tunneling capacitor but not a failure of both tunneling capacitors. 21. An embedded memory, comprising: one or more dual-polarity non-volatile memory cells, wherein a first dual-polarity non-volatile memory cell includes: a sense mode component to communicate information stored in the dual-polarity non-volatile memory cell during a read operation; and a charge mode component to facilitate storing of the information stored in the dual-polarity non-volatile memory cell, the charge mode component including a first coupling capacitor in a first well and a first tunneling capacitor in a second well. 22. The embedded memory of claim 21, wherein the charge mode component further includes a second coupling capacitor in the first well and a second tunneling capacitor in the second well. 23. The embedded memory of claim 22, wherein one node of the first coupling capacitor is electrically connected to one node of the second tunneling capacitor. 24. The embedded memory of claim 22, wherein one node of the first tunneling capacitor is electrically connected to one node of the second coupling capacitor. 25. The embedded memory of claim 21, wherein at least one or more of the dual-polarity non-volatile memory cells further include: a first floating gate having at least seventy percent of the floating gate N+doped and one ore more partitioned areas of the floating gate are P+ doped. 26. The embedded memory of claim 21, wherein at least one or more of the dual-polarity non-volatile memory cells further include: a floating gate; a P+ doped region abutted to a N+ doped region, the floating gate surrounded by the P+ doped region abutted to the N+ doped region. 27. The embedded memory of claim 21, wherein the sense mode component comprises a first read transistor and a second read transistor. 28. The embedded memory of claim 27, further comprising: a sense amplifier connected to the sense mode component. 29. The embedded memory of claim 28, wherein the sense amplifier further includes control circuitry to sense the dual-polarity non-volatile memory cell in both a differential sensing mode and in a single mode. 30. The integrated circuit of claim 22, wherein the second coupling capacitor stores a charge opposite in polarity to the charge stored in the first coupling capacitor. 31. A memory, comprising: one or more dual-polarity non-volatile memory (DPNVM) cells, a first dual-polarity non-volatile memory cell includes: a sense mode component to communicate information stored in the dual-polarity non-volatile memory cell during a read operation; and a charge mode component to facilitate storing of the information stored in the dual-polarity non-volatile memory cell, the charge mode component including a first coupling capacitor in a first well, a first tunneling capacitor in a second well, and a second coupling capacitor in the second well. 32. The integrated circuit of claim 31, wherein a plurality of the dual-polarity non-volatile memory cells share a single sense amplifier. 33. The memory of claim 31, wherein one node of the second coupling capacitor is electrically connected to one node of the first tunneling capacitor. 34. A machine-readable medium that stores data representing a memory that includes: one or more dual-polarity non-volatile memory cells, a first dual-polarity non-volatile memory cell includes: a sense mode component to communicate information stored in the dual-polarity non-volatile memory cell during a read operation; and a charge mode component to facilitate storing of the information stored in the dual-polarity non-volatile memory cell, the charge mode component including a first coupling capacitor in a first well, a first tunneling capacitor in a second well, and a second coupling capacitor in the second well. 35. The machine readable medium of claim 34, wherein the machine readable medium comprises a memory compiler to provide a layout utilized to generate one or more lithographic masks used in the fabrication of the memory. 36. Original) The machine-readable medium of claim 34, wherein the memory is an embedded memory. 37. The machine-readable medium of claim 34, wherein the dual-polarity non-volatile memory cell further comprises a sense amplifier connected to the sense mode component. 38. The machine-readable medium of claim 37, wherein the sense amplifier is capable of providing a valid read of the information stored in the non-volatile memory cell under conditions where one of the coupling capacitors is significantly more leaky than the other coupling capacitor. 39. The machine readable medium of claim 35, wherein the one or more lithographic masks are utilized during a Complementary Metal Oxide Semiconductor logic process employing equal or less than 1.0 micron technology. 40. A machine readable medium that stores data representing an integrated circuit, comprising: one or more dual-polarity non-volatile memory cells, wherein a first dual-polarity non-volatile memory cell includes: a first coupling capacitor having a first plate; a first tunneling capacitor having a second plate; a first read transistor connected to the first coupling capacitor and the first tunneling capacitor; a second coupling capacitor having a third plate, wherein the third plate of the second coupling capacitor is electrically connected to the second plate of the first tunneling capacitor; and a second tunneling capacitor having a fourth plate, wherein the fourth plate of the second tunneling capacitor is electrically connected to a first plate of the first coupling capacitor. 41. The machine readable medium of claim 40, wherein the machine readable medium comprises a memory compiler to provide a layout utilized to generate one or more lithographic masks used in the fabrication of the memory. 42. The machine-readable medium of claim 40, wherein the memory is an embedded memory. 43. The machine readable medium of claim 40, wherein the dual-polarity non-volatile memory cell further comprises a sense amplifier having a first input connected to the first read transistor and a second input connected to the second read transistor. 44. The machine readable medium of claim 41, wherein the one or more lithographic masks are utilized during a Complementary Metal Oxide Semiconductor logic process employing equal or less than 1.0 micron technology. 45. The machine readable medium of claim 40, wherein the first coupling capacitor and the second tunneling capacitor are located in a first well. 46. A method of designing a dual-polarity non-volatile memory (DPNVM) cell, the method comprising: placing a first coupling capacitor in a first well; placing a first tunneling capacitor in a second well; placing a first read transistor in a third well; connecting the gates of the first coupling capacitor, the first tunneling capacitor and the first read transistor via a floating gate in a first layer polysilicon; placing a second coupling capacitor in the second well; placing a second tunneling capacitor in the first well; placing a second read transistor in a fourth well; and connecting the gates of the second coupling capacitor, the second tunneling capacitor and the second read transistor via a floating gate in a first layer polysilicon. 47. The method of claim 46, further comprising: connecting electrically a plate of the first coupling capacitor to a plate of the second tunneling capacitor; and connecting electrically a plate of the second coupling capacitor to a plate of the first tunneling capacitor. 48. The method of claim 46, further comprising: electrically connecting a first input of a sense amplifier to the first read transistor; and electrically connecting a second input of the sense amplifier to the second read transistor. 49. An apparatus, comprising: means for placing a first coupling capacitor in a first well; means for placing a first tunneling capacitor in a second well; means for placing a first read transistor in a third well; means for connecting the gates of the first coupling capacitor, the first tunneling capacitor and the first read transistor via a floating gate in a first layer polysilicon; means for placing a second coupling capacitor in the second well; means for placing a second tunneling capacitor in the first well; means for placing a second read transistor in a fourth well; and means for connecting the gates of the second coupling capacitor, the second tunneling capacitor and the second read transistor via a floating gate in a first layer polysilicon.
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