IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0995095
(2001-11-27)
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발명자
/ 주소 |
- Gibson, Jr.,Leroy Andrew
- Griffin,Dan M.
- Horne,Lyman D.
- Sylvester,Randal R.
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출원인 / 주소 |
- L 3 Communications Corporation
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
4 인용 특허 :
4 |
초록
▼
A method and device for frame sync detection using signal combining and correlation. The method comprises the steps of despreading PN coded signals to provide in-phase I1-In, and quadrature phase Q1-Qn signals, wherein each I1-In and each Q1-Qn signal contains at least one sync bit and n≧2. Th
A method and device for frame sync detection using signal combining and correlation. The method comprises the steps of despreading PN coded signals to provide in-phase I1-In, and quadrature phase Q1-Qn signals, wherein each I1-In and each Q1-Qn signal contains at least one sync bit and n≧2. The at least one sync bit from each I1-In, and quadrature phase Q1-Qn signals are summed to form sums Is1 and Qs1, respectively. The next step provides a reference sync having at least one bit and compares each sum Is1 and Qs1 with the at least one reference bit. The results of each Is1 and Qs1 comparison are accumulated so as to form two accumulates, IA and QA, respectively. Each accumulate IA and QA, is squared to form IA2 and QA2 from which the sum IA2 and QA2 is formed. The sum IA2+QA2 is compared with a predetermined threshold and as a result of the comparison a determination of whether frame sync has been achieved is made.
대표청구항
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What is claimed is: 1. A method for frame sync detection using signal combining and correlation, the method comprising the steps of: despreading PN coded signals to provide in-phase I1-In, and quadrature phase Q1-Qn signals, wherein each I1-In and each Q1-Qn signal contains at least one sync bit a
What is claimed is: 1. A method for frame sync detection using signal combining and correlation, the method comprising the steps of: despreading PN coded signals to provide in-phase I1-In, and quadrature phase Q1-Qn signals, wherein each I1-In and each Q1-Qn signal contains at least one sync bit and where n≧2; summing the at least one sync bit from each I1-I n, and quadrature phase Q1-Qn signals to form sums Is1 and Qs1, respectively; providing a reference sync, wherein the reference sync comprises at least one bit; comparing each sum Is1 and Qs1 with the at least one bit from the reference sync; accumulating the results of each Is1 and Qs1 comparison so as to form two accumulates, IA and QA , respectively; squaring each accumulate IA and QA, respectively, to form IA2 and QA2; summing IA2 and QA2; and comparing IA2+QA2 with a predetermined threshold and as a result of the comparison, making a determination whether frame sync has been achieved is made. 2. A method as in claim 1, wherein the step of despreading PN coded signals to provide in-phase I1-In and quadrature phase Q1-Qn signals further comprises the step of letting n=20. 3. A method as in claim 1, wherein the step of summing the at least one sync bit from each I1-In and quadrature phase Q1-Qn signals to form sums Is1 and Qs1 , respectively, further comprises the step of forming sixteen sync bit sums from each I1-In and quadrature phase Q1-Qn signals. 4. A method as in claim 3, wherein the step of providing the reference sync further comprises the step of providing a sixteen-bit reference sync. 5. A method as in claim 1, wherein the step of providing the reference sync further comprises the step of storing the reference sync in a local accessible memory. 6. A method as in claim 1, wherein the step of providing the reference sync further comprises the step of receiving the reference sync from a remote source. 7. A method as in claim 1, wherein the step of summing I A2 and QA2 further comprises the steps of: performing a square root operation on the sum IA 2+QA2; and comparing the square root of the sum IA2+ QA2 with the predetermined threshold value. 8. A device comprising: a channel despreader, wherein the channel despreader provides at least two each in-phase I1-In and, quadrature phase Q1-Qn channels, where n≧2; at least one I-sync processor, wherein the at least one I-sync processor is coupled to the channel despreader, the at least one I-sync processor receiving I1-In data streams and providing an accumulated sciuared value IA as an output; at least one Q-sync processor, wherein the at least one Q-sync processor is coupled to the channel despreader, the at least one Q-sync processor receiving Q1-Qn data streams and providing an accumulated squared value QA as an output; a first summer connected to the I-sync processor and the Q-sync processor to add the accumulated squared value IA and the accumulated squared value QA to form a sum; and a comparator, wherein the comparator is coupled to the first summer and compares the sum to a predetermined threshold, wherein the comparator compares a sum from the first summer with a predetermined threshold and, as a result of the comparison, a determination whether frame sync has been achieved is made. 9. A device as in claim 8 wherein the channel despreader comprises a direct sequence spread spectrum (DSSS) despreader. 10. A device as in claim 8 wherein the channel despreader comprises a frequency hop spread spectrum (FHSS) despreader. 11. A device as in claim 8 wherein the at least one I-sync processor comprises: a first I-binary adder; a first I-memory device, the first I-memory device coupled to the first I-binary adder; a reference sync; a first I-multiplier, wherein the first I-multiplier multiplies the reference sync with the output of the first I-memory device to provide an I-multiplier result; a first I-accumulator, wherein the first accumulator comprises: a first I-register bank; a second I-adder, the second I-adder having at least two inputs, wherein one of the two inputs is coupled to an output of the first I-register bank; a second I-register bank, wherein an output of the second I-register bank is coupled to an input of the second I-adder; and a first I-squaring device, wherein the first I-squaring device is coupled to the output of the second I-register bank, wherein the first I-accumulator receives the I-multiplier result from the first I-multiplier and provides a sciuared accumulated I value. 12. A device as in claim 11 wherein the first I-binary adder comprises a two's-complement adder. 13. A device as in claim 11 wherein the first I-memory device comprises a first dual port 16횞16 RAM. 14. A device as in claim 8 wherein the at least one Q-sync processor comprises: a first Q-binary adder; a first Q-memory device, the first Q-memory device coupled to the first Q-binary adder; a first Q-multiplier, wherein the first Q-multiplier multiplies the reference sync with the output of the first Q-memory device to provide a Q-multiplier result; a first Q-accumulator, wherein the first Q-accumulator comprises: a first Q-register bank; a second Q-adder, the second Q-adder having at least two inputs, wherein one of the two inputs is coupled to an output of the first Q-register bank; a second Q-register bank, wherein an output of the second Q-register bank is coupled to an input of the second Q-adder; and a first Q-squaring device, wherein the first Q-squaring device is coupled to the output of the second Q-register device, wherein the first Q-accumulator receives the Q-multiplier result and provides a sciuared accumulated Q value. 15. A device as in claim 14 wherein the first Q-binary adder comprises a two's-complement adder. 16. A device as in claim 14 wherein the first Q-memory device comprises a first dual port 16횞16 RAM. 17. An integrated circuit (IC), wherein the integrated circuit comprises: a channel despreader, wherein the channel despreader provides at least two each in-phase I1-In and, quadrature phase Q1-Qn channels, where n≧2; at least one I-sync processor, wherein the at least one I-sync processor is coupled to the channel despreader, the at least one I-sync processor receiving I1-In data streams and providing an accumulated squared value IA as an output; at least one Q-sync processor, wherein the at least one Q-sync processor is coupled to the channel despreader, the at least one Q-sync processor receiving Q1-Qn data streams and providing an accumulated squared value QA as an output; a first summer connected to the I-sync processor and the Q-sync processor to add the accumulated squared value IA and the accumulated squared value QA to form a sum; and a comparator, wherein the comparator is coupled to the first summer and compares the sum to a predetermined threshold, wherein the comparator compares a sum from the first summer with a predetermined threshold, and as a result of the comparison, a determination whether frame sync has been achieved is made. 18. An IC as in claim 17 wherein the IC comprises an Application Specific IC (ASIC). 19. An IC as in claim 17 wherein the IC comprises a field programmable gate array (FPGA). 20. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for frame sync detection using signal combining and correlation, the method comprising the steps of: despreading PN coded signals to provide in-phase I1-In, and quadrature phase Q1-Qn signals, wherein each I1-In and each Q1-Qn signal contains at least one sync bit and where n≧2; summing the at least one sync bit from each I1-I n, and quadrature phase Q1-Qn signals to form sums Is1 and Qs1, respectively; providing a reference sync, wherein the reference sync comprises at least one bit; comparing each sum Is1 and Qs1 with the at least one bit from the reference sync; accumulating the results of each Is1 and Qs1 comparison so as to form two accumulates, IA and QA , respectively; squaring each accumulate IA and QA, respectively, to form IA2 and QA2; summing IA2 and QA2; and comparing IA2+QA2 with a predetermined threshold and as a result of the comparison, making a determination of whether frame sync has been achieved is made. 21. A program storage device as in claim 20 wherein the program of instructions comprise at least one Very High Speed Integrated Circuit (VHSIC) Hardware Description (VHDL) Language file. 22. A device as in claim 8 wherein the device provides non-coherent power detection. 23. An integrated circuit as in claim 17 wherein the device provides non-coherent power detection. 24. A device comprising: a channel despreader, wherein the channel despreader provides at least two each in-phase I1-In and, quadrature phase Q1-Qn channels, where n≧2; at least one I-sync processor, wherein the at least one I-sync processor is coupled to the channel despreader, the at least one I-sync processor receiving I1-In data streams and providing an accumulated IA squared value as an output; at least one Q-sync processor, wherein the at least one Q-sync processor is coupled to the channel despreader, the at least one Q-sync processor receiving Q1-Qn data streams and providing an accumulated QA squared value as an output; a first summer connected to the I-sync processor and the Q-sync processor to add the accumulated IA squared value and the accumulated QA squared value to form a sum; and a comparator, wherein the comparator is coupled to the first summer and compares the sum to a predetermined threshold, wherein the device provides non-coherent power detection. 25. An integrated circuit (IC), wherein the integrated circuit comprises: a channel despreader, wherein the channel despreader provides at least two each in-phase I1-In and quadrature phase Q1-Qn channels, where n≧2; at least one I-sync processor, wherein the at least one I-sync processor is coupled to the channel despreader, the at least one I-sync processor receiving I1-In data streams and providing an accumulated IA squared value as an output; at least one Q-sync processor, wherein the at least one Q-sync processor is coupled to the channel despreader, the at least one Q-sync processor receiving Q1-Qn data streams and providing an accumulated QA squared value as an output; a first summer connected to the I-sync processor and the Q-sync processor to add the accumulated IA squared value and the accumulated QA squared value to form a sum; and a comparator, wherein the comparator is coupled to the first summer and compares the sum to a predetermined threshold, wherein the integrated circuit provides non-coherent power detection.
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