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Described herein is a data processor that comprises a register memory and a processor unit. The processor unit simultaneously executes a single instruction on a plurality of operands in the register memory. The plurality of operands may be one or more contiguous regions. The contiguous regions may

Described herein is a data processor that comprises a register memory and a processor unit. The processor unit simultaneously executes a single instruction on a plurality of operands in the register memory. The plurality of operands may be one or more contiguous regions. The contiguous regions may be specified as an address and a format such as a row, a column, or a neighborhood relative to the address.

대표청구항 ▼

The invention claimed is: 1. An integrated circuit comprising: a two-dimensional register memory; and a parallel processor for executing an instruction simultaneously on a first plurality of operands in the two-dimensional register memory, wherein the instruction comprises an operation, a first add

The invention claimed is: 1. An integrated circuit comprising: a two-dimensional register memory; and a parallel processor for executing an instruction simultaneously on a first plurality of operands in the two-dimensional register memory, wherein the instruction comprises an operation, a first address of a first operand in the first plurality of operands, wherein the first operand may be located anywhere in the two-dimensional register memory, and a first configuration identifying the first plurality of operands, wherein the parallel processor executes the operation on an arbitrarily located first plurality of operands in the two-dimensional register memory. 2. The integrated circuit as claimed in claim 1, wherein an operand in the first register memory is specified by a first address in a second register memory. 3. The integrated circuit as claimed in claim 1, wherein an address of an operand in the first register memory is specified in the instruction. 4. The integrated circuit as claimed in claim 2, wherein the instruction comprises an indication of a second address relative to the first address. 5. The integrated circuit as claimed in claim 2, wherein the instruction comprises an indication of an operation, and wherein the second register memory comprises an indication of a second address relative to the first address. 6. The intearated circuit as claimed in claim 5, wherein the operation is an addition operation. 7. The integrated circuit as claimed in claim 1, wherein the first register memory is an element of a scalar unit. 8. The integrated circuit as claimed in claim 1, wherein the processor unit is a vector unit. 9. The integrated circuit of claim 1, wherein the first form of contiguous cells corresponds to a plurality of neighboring addresses, wherein each neighboring address is adjacent to the first address. 10. The integrated circuit as claimed in claim 1, wherein the first register memory comprises an array of cells, and wherein each cell in the array can be specified as a pair of coordinates. 11. The integrated circuit as claimed in claim 10, wherein each cell of the array is capable of storing 8 or more bits. 12. The integrated circuit as claimed in claim 10, wherein the array extends in two dimensions and the cells of the array are located on rows in the first dimension and columns in the second dimension. 13. The integrated circuit as claimed in claim 1, wherein the first register memory and the processor unit are arranged on the same integrated circuit. 14. The integrated circuit of claim 1, wherein the first configuration corresponds to a horizontal arrangement with respect to the first address. 15. The integrated circuit of claim 1, wherein the first configuration corresponds to a vertical arrangement with respect to the first address. 16. The integrated circuit of claim 4, wherein the second address corresponds to a horizontal arrangement with respect to the first address. 17. The integrated circuit of claim 4, wherein the second address corresponds to a vertical arrangement with respect to the first address. 18. The integrated circuit of claim 4, wherein the second address corresponds to a plurality of neighboring addresses, wherein each neighboring address is adjacent to the first address. 19. The integrated circuit of claim 1, wherein the operation is performed on the first plurality of operands and a second plurality of operands, and wherein the instruction further comprises a second address of a second operand in the second plurality of operands and a second configuration of the second plurality of operands.