IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0856476
(2004-05-29)
|
발명자
/ 주소 |
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
6 인용 특허 :
101 |
초록
▼
A high speed data communication system uses a single-ended bus architecture with a reference signal extracted from a differential periodic signal that is transmitted along with single-ended data. By using a periodic signal such a clock signal with approximately 50% duty cycle, a much more stable and
A high speed data communication system uses a single-ended bus architecture with a reference signal extracted from a differential periodic signal that is transmitted along with single-ended data. By using a periodic signal such a clock signal with approximately 50% duty cycle, a much more stable and accurate reference signal is established for receiving single-ended data.
대표청구항
▼
What is claimed is: 1. A receiver, comprising: a first buffer that is operable to receive a first signal and to process the first signal thereby generating a reference signal, wherein the first signal is a differential signal; and a second buffer that is operable to receive a second signal and to c
What is claimed is: 1. A receiver, comprising: a first buffer that is operable to receive a first signal and to process the first signal thereby generating a reference signal, wherein the first signal is a differential signal; and a second buffer that is operable to receive a second signal and to compare a level of the second signal to the reference signal to determine a logic level of the second signal. 2. The receiver of claim 1, wherein: the second signal is a single-ended signal. 3. The receiver of claim 1, wherein: the first signal is a differential clock signal; and the second signal is a single-ended data signal. 4. The receiver of claim 1, wherein: the second buffer includes a differential pair that includes: a current source; a first differential NMOS transistor having a source, gate, and drain, wherein the source of the first differential NMOS transistor is coupled to the current source; a second differential NMOS transistor having a source, gate, and drain, wherein the source of the second differential NMOS transistor is coupled to the current source; the second signal is provided to the gate of the second differential NMOS transistor; and a buffered version of the second signal is output from the drain of the second differential NMOS transistor. 5. The receiver of claim 4, wherein: a first resistor is communicatively coupled from the gate of the first differential transistor to a first voltage level; a second resistor is communicatively coupled from the gate of the first differential transistor to a second voltage level; a third resistor is communicatively coupled from the gate of the second differential transistor to the first voltage level; and a fourth resistor is communicatively coupled from the gate of the second differential transistor to the second voltage level. 6. The receiver of claim 1, wherein: the second buffer includes a differential pair that includes: a current source; a first differential NMOS transistor having a source, gate, and drain, wherein the source of the first differential NMOS transistor is coupled to the current source; a second differential NMOS transistor having a source, gate, and drain, wherein the source of the second differential NMOS transistor is coupled to the current source; a buffered version of the second signal is provided to the gate of the second differential NMOS transistor; the reference signal is provided to the gate of the first differential NMOS transistor; the logic level of the second signal corresponds to a voltage level at the drain of the second differential NMOS transistor. 7. The receiver of claim 1, wherein: the first buffer includes a differential pair that includes: a current source; a first differential NMOS transistor having a source, gate, and drain, wherein the source of the first differential NMOS transistor is coupled to the current source; a second differential NMOS transistor having a source, gate, and drain, wherein the source of the second differential NMOS transistor is coupled to the current source; a first differential component of the differential signal is provided to the gate of the first differential NMOS transistor; a second differential component of the differential signal is provided to the gate of the second differential NMOS transistor; and a buffered, single-ended signal that corresponds to the first signal is output from the drain of the second differential NMOS transistor. 8. The receiver of claim 7, wherein: the first buffer includes a filter that filters the buffered, single-ended signal that corresponds to the first signal thereby extracting a DC level of the first signal there from. 9. The receiver of claim 1, wherein: the first buffer includes a differential pair that includes: a current source; a first differential NMOS transistor having a source, gate, and drain, wherein the source of the first differential NMOS transistor is coupled to the current source; a second differential NMOS transistor having a source, gate, and drain, wherein the source of the second differential NMOS transistor is coupled to the current source, and wherein the gate and the drain of the second differential NMOS transistor are communicatively coupled; a DC level that corresponds to the first signal is provided to the gate of the first differential NMOS transistor; and the reference signal is output from the gate or the drain of the second differential NMOS transistor. 10. The receiver of claim 1, further comprising: a third buffer that is operable to receive a third signal and to compare a level of the third signal to the reference signal to determine a logic level of the third signal. 11. A communication system, comprising: a transmitter that is operable to transmit a first signal and a second signal, wherein the first signal is a differential signal; a receiver that includes a first buffer and a second buffer; wherein the transmitter and the receiver are communicatively coupled via a bus; wherein the first buffer is operable to receive the first signal from the bus and to process the first signal thereby generating a reference signal; and wherein the second buffer is operable to receive the second signal from the bus and to compare a level of the second signal to the reference signal to determine a logic level of the second signal. 12. The communication system of claim 11, wherein: the bus is operable to convey at least one differential signal and at least one single-ended signal; and the second signal is a single-ended signal. 13. The communication system of claim 11, wherein: the bus is operable to convey at least one differential signal and at least one single-ended signal; the first signal is a differential clock signal; and the second signal is a single-ended data signal. 14. The communication system of claim 11, wherein: the second buffer includes a first differential pair that includes: a current source; a first differential NMOS transistor having a source, gate, and drain, wherein the source of the first differential NMOS transistor is coupled to the current source; a second differential NMOS transistor having a source, gate, and drain, wherein the source of the second differential NMOS transistor is coupled to the current source; the second buffer includes a second differential pair that includes: a current source; a first differential NMOS transistor having a source, gate, and drain, wherein the source of the first differential NMOS transistor is coupled to the current source; a second differential NMOS transistor having a source, gate, and drain, wherein the source of the second differential NMOS transistor is coupled to the current source; the second signal is provided to the gate of the second differential NMOS transistor of the first differential pair; a buffered version of the second signal is output from the drain of the second differential NMOS transistor of the first differential pair and is provided to the gate of the second differential NMOS transistor of the second differential pair; the reference signal is provided to the gate of the first differential NMOS transistor of the second differential pair; the logic level of the second signal corresponds to a voltage level at the drain of the second differential NMOS transistor of the second differential pair. 15. The communication system of claim 11, wherein: the second signal is a single-ended signal; the first buffer includes a first differential pair that includes: a current source; a first differential NMOS transistor having a source, gate, and drain, wherein the source of the first differential NMOS transistor is coupled to the current source; a second differential NMOS transistor having a source, gate, and drain, wherein the source of the second differential NMOS transistor is coupled to the current source; the first buffer includes a second differential pair that includes: a current source; a first differential NMOS transistor having a source, gate, and drain, wherein the source of the first differential NMOS transistor is coupled to the current source; a second differential NMOS transistor having a source, gate, and drain, wherein the source of the second differential NMOS transistor is coupled to the current source, and wherein the gate and the drain of the second differential NMOS transistor of the second differential pair are communicatively coupled; a first differential component of the differential signal is provided to the gate of the first differential NMOS transistor of the first differential pair; a second differential component of the differential signal is provided to the gate of the second differential NMOS transistor of the first differential pair; a buffered, single-ended signal that corresponds to the first signal is output from the drain of the second differential NMOS transistor of the first differential pair; the first buffer includes a filter that filters the buffered, single-ended signal that corresponds to the first signal thereby extracting a DC level of the first signal there from; the DC level of the first signal is provided to the gate of the first differential NMOS transistor of the second differential pair; and the reference signal is output from the gate or the drain of the second differential NMOS transistor of the second differential pair. 16. The communication system of claim 11, wherein: the receiver includes a third buffer that is operable to receive a third signal and to compare a level of the third signal to the reference signal to determine a logic level of the third signal. 17. An integrated circuit, comprising: a first functional block that is operable to receive a first signal and to process the first signal thereby generating a second signal, wherein the first signal is a differential signal; a second functional block that is operable to receive a third signal and to process the third signal thereby generating a fourth signal; and wherein the second functional block is operable to compare the fourth signal and the second signal to determine bit values within the third signal. 18. The integrated circuit of claim 17, wherein: the first signal is a substantially periodic differential signal; and the first functional block includes a first differential pair that receives and buffers the first signal thereby generating a first single-ended output signal; the first functional block includes a filter that filters the first single-ended output signal thereby extracting a DC level of the first signal there from; and the first functional block includes a second differential pair that uses the DC level of the first signal to generate the second signal. 19. The integrated circuit of claim 17, wherein: the third signal is a single-ended signal; and the second functional block includes a first differential pair that receives and buffers the third signal thereby generating the fourth signal; and the second functional block includes a second differential pair that is operable to compare the fourth signal and the second signal to determine bit values within the third signal. 20. The integrated circuit of claim 17, wherein: the first signal is a substantially periodic differential signal; the second signal is a DC voltage level that corresponds to the substantially periodic differential signal; the third signal is a single-ended data signal; and the fourth signal is a buffered version of the third signal.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.