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A programmable logic device (PLD) is provided that includes at least one dedicated output routing channel configured to facilitate the processing of output signals generated by multiple function-specific blocks (FSBs). The output routing channel includes a plurality of functional units that may be p

A programmable logic device (PLD) is provided that includes at least one dedicated output routing channel configured to facilitate the processing of output signals generated by multiple function-specific blocks (FSBs). The output routing channel includes a plurality of functional units that may be programmably selectively chained, wherein each functional unit contains an operational block and output selection logic that are configured to programmably selectively implement any of a variety of operations (e.g., bitwise, logical, arithmetic, etc.) that may be performed on the outputs of single FSBs and/or several FSBs. In addition to the output routing channel, the PLD may also contain at least one input routing channel that is configured to facilitate the routing, registering, and/or selection of FSB input signals. In some cases, the FSB input routing channel may also include circuitry for performing elementary processing operations.

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What is claimed is: 1. A programmable logic device, comprising: a plurality of programmable logic block means disposed on the device in a two-dimensional array of intersecting rows and columns; a plurality of function-specific block means (FSB means) arranged in an additional column included withi

What is claimed is: 1. A programmable logic device, comprising: a plurality of programmable logic block means disposed on the device in a two-dimensional array of intersecting rows and columns; a plurality of function-specific block means (FSB means) arranged in an additional column included within the two-dimensional array, wherein each FSB means includes means at least partly hardwired to perform a specific function on at least one multi-bit FSB input signal to generate at least one multi-bit FSB output signal, and further includes input processing block means to process input signals; and for at least one pair of adjacent FSB means in said additional column, dedicated connection means between respective input processing block means of the FSB means in said pair. 2. The programmable logic device of claim 1 wherein each said input processing block means comprises: at least one register means; and at least one programmable logic connector means; whereby: said input processing block means performs at least one of: (a) passing or buffering of input signals; (b) selectively registering signals; and (c) selecting between several possible input signals. 3. The programmable logic device of claim 1 wherein each said FSB means comprises at least one multiplier means. 4. The programmable logic device of claim 3 wherein each said input processing block means comprises: at least one register means; and at least one programmable logic connector means; whereby: said input processing block means performs at least one of: (a) passing or buffering of input signals; (b) selectively registering signals; and (c) selecting between several possible input signals. 5. A programmable logic device, comprising: a plurality of programmable logic block means disposed on the device in a two-dimensional array of intersecting rows and columns; a plurality of function-specific block means (FSB means) arranged in an additional column included within the two-dimensional array, wherein each FSB means includes means at least partly hardwired to perform a specific function on at least one multi-bit FSB input signal to generate at least one multi-bit FSB output signal, and further includes functional means to process said at least one output signal of said FSB means; and for at least one pair of adjacent FSB means in said additional column, dedicated connection means between respective functional means of the FSB means in said pair. 6. The programmable logic device of claim 5 wherein each said functional means comprises: at least one adder means; at least one register means; and at least one programmable logic connector means; whereby: said functional means performs at least one of: (a) accumulating of FSB output signals; (b) selectively registering signals; and (c) selecting between several possible output signals. 7. The programmable logic device of claim 5 wherein each said FSB means comprises at least one multiplier means. 8. The programmable logic device of claim 7 wherein each said functional means comprises: at least one adder means; at least one register means; and at least one programmable logic connector means; whereby: said functional unit performs at least one of: (a) accumulating of FSB output signals; (b) selectively registering signals; and (c) selecting between several possible output signals. 9. A programmable logic device, comprising: a plurality of programmable logic block means disposed on the device in a two-dimensional array of intersecting rows and columns; a plurality of multiplier means arranged in an additional column included within the two-dimensional array; and means for performing processing operations on output signals generated by the plurality of multiplier means, wherein: the means for performing the processing operations are included in an output routing channel means that extends along the plurality of multiplier means; the output routing channel means includes means for selectively adding output signals generated by the plurality of multiplier means, and means for selectively feeding back the added output signals to the plurality of multiplier means; the means for selectively adding and the means for selectively feeding back are programmably selectively configurable for operation in a plurality of modes, wherein in a first mode, the means for selectively adding and the means for selectively feeding back are programmably selectively configurable to process the output signals as an infinite-impulse response filter. 10. A programmable logic device, comprising: a plurality of programmable logic block means disposed on the device in a two-dimensional array of intersecting rows and columns; general interconnection resource means configured to convey signals amongst the plurality of programmable logic block means; a plurality of function-specific block means (FSB means) arranged in an additional column included within the two-dimensional array, wherein each FSB means includes means at least partly hardwired to perform a specific function on at least one multi-bit FSB input signal to generate at least one multi-bit FSB output signal; and an input routing channel means extending along the plurality of FSB means, wherein the input routing channel means contains a plurality of input processing block means, each input processing block means being associated with a respective one of the FSBs and being configured to programmably selectively accept at least one signal from the general interconnection resource means and to generate at least one multi-bit FSB input signal to be conveyed to an associated FSB means. 11. The device defined in claim 10, wherein each input processing block means contains registering and selection logic means, wherein the registering and selection logic means is configured to programmably selectively generate registered multi-bit FSB input signals. 12. The device defined in claim 11, wherein each input processing block means further contains processing means configured to perform logic operations on at least one signal accepted from the general interconnection resource means to generate at least one multi-bit FSB input signal. 13. The device defined in claim 11, wherein the input routing channel means further contains common routing resource means that span adjacent to the plurality of input processing block means, wherein the common routing resource means is programmably selectively connectable to the registering and selection logic means within each input processing block means. 14. The device defined in claim 11, wherein the registering and selection logic means includes a plurality of registering and selection means, each said registering means and selection means being independently programmably controllable. 15. A programmable logic device, comprising: a plurality of programmable logic block means disposed on the device in a two-dimensional array of intersecting rows and columns; a plurality of multiplier means arranged in an additional column included within the two-dimensional array, wherein each multiplier means includes means that is at least partly hardwired to multiply a plurality of multi-bit input signals to generate a multi-bit output signal; general interconnection resource means configured to convey signals amongst the plurality of programmable logic block means; and an input routing channel means extending along the plurality of multiplier means, wherein the input routing channel means contains a plurality of input processing block means, each input processing block means being associated with a respective one of the multiplier means and being configured to programmably selectively accept signals from the general interconnection resource means and to generate an associated plurality of multi-bit input signals to be conveyed to its associated multiplier means. 16. The device defined in claim 15, wherein each input processing block means contains registering and selection logic means, wherein the registering and selection logic means is configured to programmably selectively generate registered multi-bit multiplier input signals. 17. The device defined in claim 16, wherein: the registering and selection logic means is further configured to programmably select between an unregistered and a registered version of a respective multiplier input signal to be conveyed as an input signal to an adjacent multiplier means; the device further comprising: an output routing channel means extending along the plurality of multiplier means, wherein: the output routing channel means is programmably configurable to perform processing operations on the multi-bit output signals generated by the plurality of multiplier means; the output routing channel means contains a plurality of adder means arranged in a programmably selectively-chainable adder chain means, wherein each adder means is configured to add a first adder input signal to a second adder input signal to generate an adder output signal; the output routing channel means further includes programmable input/output selection means between each pair of adder means in the adder chain means, wherein the programmable input/output selection means is configured to programmably selectively pass an associated adder output signal of a first adder means in the pair to a second adder means in the pair as an associated first adder input signal for the second adder means; and the programmable input/output selection means between each pair of adder means includes register means configured to register the associated adder output signal generated by the first adder means, and wherein the programmable input/output selection means is further configured to programmably select between an unregistered and a registered version of the associated adder output signal of the first adder means to be conveyed as the associated first adder input signal to the second adder means. 18. The device defined in claim 17, wherein the registering and selection logic means is further configured such that, for at least one multiplier means, the registered version of the respective multiplier input signal is delayed by two register delays. 19. The device defined in claim 15, wherein the registering and selection logic means includes a plurality of registering and selection means, each said registering means and selection means being independently programmably controllable. 20. The device defined in claim 15, wherein the input routing channel means contains a common input bus means that spans adjacent to and is programmably selectively connectable to the plurality of input processing block means, and wherein the common input bus means includes registering and selection means configured to programmably selectively convey registered data to each input processing block means. 21. The device defined in claim 20, further comprising a feedback conductor means configured to convey results from the processing operations performed in the output routing channel means to the common input bus means.