초록 ▼

A circuit for assisting signal transitions on a wire, and a method thereof. The circuit includes a first subcircuit that causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and then turn off. The first transistor drives the output to a high state t

A circuit for assisting signal transitions on a wire, and a method thereof. The circuit includes a first subcircuit that causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and then turn off. The first transistor drives the output to a high state to assist in the rising transition. The circuit also includes a second subcircuit that causes a second transistor that is coupled to the circuit's output to turn on during a falling transition and then turn off. The second transistor drives the output to a low state to assist in the falling transition.

대표청구항 ▼

What is claimed is: 1. A circuit for assisting signal transitions on a wire, said circuit comprising: first circuitry coupled to said wire, said first circuitry causing a first transistor to turn on in response to a rising transition of a signal on said wire and then turn off after a first period o

What is claimed is: 1. A circuit for assisting signal transitions on a wire, said circuit comprising: first circuitry coupled to said wire, said first circuitry causing a first transistor to turn on in response to a rising transition of a signal on said wire and then turn off after a first period of time, said first transistor driving the output of said circuit to a high state to assist in said rising transition; second circuitry coupled to said wire, said second circuitry causing a second transistor to turn on in response to a falling transition of a signal on said wire and then turn off after a second period of time, said second transistor driving said output to a low state to assist in said falling transition; and third circuitry coupled to said wire, said third circuitry for maintaining said high state at said output from said rising transition until said falling transition after said first transistor turns off, said third circuitry also for maintaining said low state from said falling transition until a next rising transition after said second transistor turns off. 2. The circuit of claim 1 wherein said third circuitry comprises a plurality of gates. 3. The circuit of claim 1 wherein the input of said circuit is connected to said output and wherein said input and output are coupled to said wire in a lookaside configuration. 4. The circuit of claim 1 wherein said first circuitry comprises: a NAND gate coupled to said wire; and a delay chain coupled to said NAND gate. 5. The circuit of claim 1 wherein said first transistor is a p-type device. 6. The circuit of claim 1 wherein said second circuitry comprises: a NOR gate coupled to said wire; and a delay chain coupled to said NOR gate. 7. The circuit of claim 1 wherein said second transistor is an n-type device. 8. In a circuit coupled to a wire, a method of assisting signal transitions on said wire, said method comprising: receiving a rising input at said circuit indicating a rising transition on said wire, said rising input causing a first transistor to turn on for a first period of time to drive the output of said circuit to a high state to assist said rising transition, said first transistor turning off after said first period of time; receiving a falling input at said circuit indicating a falling transition on said wire, said falling input causing a second transistor to turn on for a second period of time to drive said output to a low state to assist said falling transition, said second transistor turning off after said second period of time; maintaining said output in said high state after said rising transition and after said first transistor turns off and until a respective falling transition; and maintaining said output in said low state after said falling transition and after said second transistor turns off and until a next rising transition. 9. The method of claim 8 wherein said first transistor is coupled to circuitry comprising; a NAND gate coupled to said wire; and a delay chain coupled to said NAND gate. 10. The method of claim 8 wherein said first transistor is a p-type device. 11. The method of claim 8 wherein said second transistor is coupled to circuitry comprising: a NOR gate coupled to said wire; and a delay chain coupled to said NOR gate. 12. The method of claim 8 wherein said second transistor is an n-type device. 13. The method of claim 8 wherein said circuit comprises a plurality of series-connected gates coupled between the input of said circuit and said output. 14. The method of claim 8 wherein the input of said circuit is connected to said output and wherein said input and output are coupled to said wire in a lookaside configuration. 15. A device comprising: a wire for propagating a signal; and a circuit coupled to said wire, said circuit having an input and an output, said circuit causing a first transistor to turn on and then turn off, said first transistor driving said output to a first state in response to said circuit detecting a first transition in said signal, said circuit maintaining said first state at said output with said first transistor turned off until a second transition is detected in said signal, wherein in response to said circuit detecting said second transition said circuit causes a second transistor to turn on and then turn off, said second transistor driving said output to a second state, and said circuit maintaining said second state at said output with said second transistor turned off until a third transition is detected in said signal. 16. The device of claim 15 wherein said circuit comprises a plurality of series-connected gates coupled between said input and said output. 17. The device of claim 15 wherein said input is connected to said output and wherein said input and output are coupled to said wire in a lookaside configuration. 18. The device of claim 15 wherein said circuit comprises: first circuitry coupled to said input, said first circuitry causing said first transistor that is coupled to said output to turn on during said first transition and then turn off after a first period of time, said first transistor driving said output to said first state to assist in said first transition; and second circuitry coupled to said input, said second circuitry causing said second transistor that is coupled to said output to turn on during said second transition and then turn off after a second period of time, said second transistor driving said output to said second state to assist in said second transition. 19. The device of claim 18 wherein said first transition is a rising transition, said first state is a high state, said second transition is a falling transition and said second state is a low state. 20. The device of claim 19 wherein said first circuitry comprises a NAND gate coupled to said input and a delay chain, wherein said first transistor is a p-type device, and wherein said second circuitry comprises a NOR gate coupled to said input and a delay chain, and wherein said second transistor is an n-type device. 21. The device of claim 18 wherein said first transition is a falling transition, said first state is a low state, said second transition is a rising transition and said second state is a high state. 22. The device of claim 21 wherein said first circuitry comprises a NOR gate coupled to said input and a delay chain, wherein said first transistor is an n-type device, and wherein said second circuitry comprises a NAND gate coupled to said input and a delay chain, and wherein said second transistor is a p-type device.