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Multilevel fair priority round robin arbiter 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
출원번호 US-0335577 (2002-12-31)
발명자 / 주소
  • Chaudhari,Sunil C.
  • Liu,Jonathan W.
  • Patel,Manan
  • Duresky,Nicholas E.
출원인 / 주소
  • Intel Corporation
인용정보 피인용 횟수 : 51  인용 특허 : 16

초록

A method and apparatus for controlling access to a plurality of resources based on multiple received requests is provided. The system includes a priority register configured to receive each individual request, determine a priority for the request, and transmit the request to a priority appropriate

대표청구항

What is claimed is: 1. A system for controlling access to a plurality of resources based on at least one individual request received from at least one requestor seeking access to said resources, comprising: a priority register configured to receive each individual request and determine a priority f

이 특허에 인용된 특허 (16)

  1. Buch Bruce D. (Westborough MA) MacGregor Cecil D. (Milford MA), Arbiter with programmable dynamic request prioritization.
  2. Malmquist Carl A. (Vestal NY) Wilson John D. (Matthews NC), Arbitration apparatus for determining priority of access to a shared bus on a rotating priority basis.
  3. Sato Masami (Ishikawa JPX) Goto Yuichi (Kawasaki JPX), Bus arbiter and bus arbitrating method.
  4. Hadwiger, Rainer R.; Krivacek, Paul D.; Sørensen, Jørn; Birk, Palle, Bus arbitration method employing a table of slots suitably distributed amongst bus masters.
  5. Pham Thai H., Cascaded round robin request selection method and apparatus.
  6. McKinney Steven J. (Coral Springs FL) Earnshaw William E. (N. Lauderdale FL), Dual rotating priority arbitration method for a multiprocessor memory bus.
  7. Dotson, Gary Dan, Group shifting and level shifting rotational arbiter system.
  8. Shenderovich, Georgiy, Multi-level and multi-resolution bus arbitration.
  9. Creedon Tadhg,IEX ; Gahan Richard A.,IEX ; Morgan Fearghal,IEX, Multi-level round robin arbitration system.
  10. Whittaker Bruce E. (Mission Viejo CA) Barajas Saul (Capistrano Beach CA) Watson Leland E. (Mission Viejo CA), Multiprocessor multifunction arbitration system with two levels of bus access including priority and normal requests.
  11. Gallagher Patrick W. (Vestal NY), Overriding programmable priority and selective blocking in a computer system.
  12. Gehman Judy M., Priority arbiter with shifting sequential priority scheme.
  13. Narayanan C. Murali (Wheaton IL) Zee Benjamin (Oak Park IL), Programmable memory-based arbitration system for implementing fixed and flexible priority arrangements.
  14. O\Connell Anne (Galway IEX) Creedon Tadhg (Galway IEX) Smith Deidre A. (Kildare IEX), Programmable priority arbiter.
  15. Vernon Mary K. (Madison WI) Manber Udi (Tuscon AZ), Round-robin protocol method for arbitrating access to a shared bus arbitration providing preference to lower priority un.
  16. Li-Jau Steven Yang, Single cycle modified round-robin arbitration with embedded priority.

이 특허를 인용한 특허 (51)

  1. Osano, Hidekazu; Kinoshita, Takayuki; Iwami, Yoshikazu; Hataida, Makoto, Arbitration device that arbitrates conflicts caused in data transfers.
  2. Okada, Masaki, Arbitration device, arbitration method, and electronic apparatus.
  3. Naylor, Rowan Nigel, Arbitration in multiprocessor device.
  4. Nishikawa,Tomoki, Arbitration method and device.
  5. Law, Patrick Y., Arbitration unit for memory system.
  6. Gara, Alan G.; Chen, Dong; Heidelberger, Philip; Ohmacht, Martin, Combined group ECC protection and subgroup parity protection.
  7. Gara, Alan; Chen, Dong; Heidelberger, Philip; Ohmacht, Martin, Combined group ECC protection and subgroup parity protection.
  8. Gara, Alan; Chen, Dong; Heidelberger, Philip; Ohmacht, Martin, Combined group ECC protection and subgroup parity protection.
  9. Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Heidelberger, Philip; Steinmacher-Burow, Burkhard; Vranas, Pavlos, DMA engine for repeating communication patterns.
  10. Gara, Alan G.; Marcella, James A.; Ohmacht, Martin, Data eye monitor method and apparatus.
  11. Danilak, Radoslav; Rao, Krishnaraj S., Disk controller for implementing efficient disk I/O for a computer system.
  12. Gara, Alan G.; Chen, Dong; Coteus, Paul W.; Flynn, William T.; Marcella, James A.; Takken, Todd; Trager, Barry M.; Winograd, Shmuel, Error correcting code with chip kill capability and power saving enhancement.
  13. Chen, Dong; Gara, Alan; Heidelberger, Philip; Ohmacht, Martin; Vranas, Pavlos, Extended write combining using a write continuation hint flag.
  14. Chen, Dong; Heidelberger, Phillip; Vranas, Pavlos, Hardware packet pacing using a DMA in a parallel computer.
  15. Danilak, Radoslav; Rao, Krishnaraj S., Hardware support system for accelerated disk I/O.
  16. Danilak, Radoslav; Rao, Krishnaraj S., Hardware support system for accelerated disk I/O.
  17. Chiu, Gordon Raymond; Freeman, John Stuart, Hierarchical arbitration.
  18. Prasadh, Ramamoorthy Guru, Integrated circuit having a bus network, and method for the integrated circuit.
  19. Prasadh, Ramamoorthy Guru, Integrated circuit having a bus network, and method for the integrated circuit.
  20. Almasi, Gheorghe; Dozsa, Gabor; Kumar, Sameer, Mechanism to support generic collective communication across a variety of programming models.
  21. Danilak, Radoslav, Memory controller for non-sequentially prefetching data for a processor of a computer system.
  22. Danilak, Radoslav, Memory controller for sequentially prefetching data for a processor of a computer system.
  23. Blocksome, Michael; Chen, Dong; Giampapa, Mark E.; Heidelberger, Philip; Kumar, Sameer; Parker, Jeffrey J., Message passing with a limited number of DMA byte counters.
  24. Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Heidelberger, Philip; Ohmacht, Martin; Salapura, Valentina; Vranas, Pavlos, Method and apparatus for efficiently tracking queue entries relative to a timestamp.
  25. Blumrich, Matthias A.; Salapura, Valentina, Method and apparatus for granting processors access to a resource.
  26. Blumrich, Matthias A.; Salapura, Valentina, Method and apparatus for single-stepping coherence events in a multiprocessor system under software control.
  27. Gara, Alan; Ohmacht, Martin; Salapura, Valentina; Sugavanam, Krishnan; Hoenicke, Dirk, Method and apparatus of prefetching streams of varying prefetch depth.
  28. Bellofatto, Ralph E.; Ellavsky, Matthew R.; Gara, Alan G.; Giampapa, Mark E.; Gooding, Thomas M.; Haring, Rudolf A.; Hehenberger, Lance G.; Ohmacht, Martin, Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan.
  29. Danilak, Radoslav; Rao, Krishnaraj S., Method and system for dynamic buffering of disk I/O command chains.
  30. Pathak,Akshay; Phung,Quang, Method and system for n dimension arbitration algorithm--scalable to any number of end points.
  31. Mittal, Aditya, Method and system of reducing latencies associated with resource allocation by using multiple arbiters.
  32. Reinig, Helmut; Sonntag, Soeren, Method for operating a plurality of arbiters and arbiter system.
  33. Gish,David W.; Massa,Don V., Method, system, and apparatus for an adaptive weighted arbiter.
  34. Berger, Deanna Postles Dunn; Ambroladze, Ekaterina M.; Fee, Michael; Orf, Diana Lynn, Multiple level linked LRU priority.
  35. Jensen, Michael Gottlieb; Kinter, Ryan C., Multithreading instruction scheduler employing thread group priorities.
  36. Jensen, Michael Gottlieb; Kinter, Ryan C., Multithreading instruction scheduler employing thread group priorities.
  37. Chen, Dong; Gabor, Dozsa; Giampapa, Mark E.; Heidelberger, Phillip, Optimized collectives using a DMA on a parallel computer.
  38. Bulusu, Ravi P.; Ghosh, Subir K., Prefetch mechanism for bus master memory access.
  39. Mittal, Aditya; Kanuri, Mrudula; Malladi, Venkata, Priority based bus arbiters avoiding deadlock and starvation on buses that support retrying of transactions.
  40. Okada, Masaki, Processor and control method for processor.
  41. Blumrich, Matthias A.; Salapura, Valentina, Programmable partitioning for high-performance coherence domains in a multiprocessor system.
  42. Henriksson, Tomas; Steffens, Elisabeth Francisca Maria, Resource controlling with dynamic priority adjustment.
  43. Hiratzka,T. Douglas; Limondin,Philippe M.; Bortz,Mark A., Rotating priority queue manager.
  44. Chiu, George; Gara, Alan G.; Salapura, Valentina, Shared performance monitor in a multiprocessor system.
  45. Chiu, George; Gara, Alan G.; Salapura, Valentina, Shared performance monitor in a multiprocessor system.
  46. Tardieux, Jean-Louis; Soerensen, Joern, Shared resource arbitration.
  47. Yamaguchi, Yasuhiko; Sugimoto, Sadahiro, Storage system with performance limit detection unit and processing percentage determination unit for ensuring priority data performance.
  48. Toksvig, Michael; Lindholm, Erik, System and method for deadlock-free pipelining.
  49. Toksvig, Michael; Lindholm, Erik, System and method for deadlock-free pipelining.
  50. Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Hoenicke, Dirk; Ohmacht, Martin; Salapura, Valentina; Sugavanam, Krishnan, System and method for programmable bank selection for banked memory subsystems.
  51. Steffens, Elisabeth Francisca Maria; Henriksson, Tomas, Systems and methods for resource controlling.
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