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A computer system having a plurality of parallel execution pipelines which may generate data for storing in a memory, data from the pipelines may be stored in a queue prior to accessing the memory and the system includes circuitry for reordering data from the different pipelines before inserting ont

A computer system having a plurality of parallel execution pipelines which may generate data for storing in a memory, data from the pipelines may be stored in a queue prior to accessing the memory and the system includes circuitry for reordering data from the different pipelines before inserting onto the queue.

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The invention claimed is: 1. A computer system having a memory, a data unit comprising a first parallel execution pipeline in a first slot of the data unit and a second parallel execution pipeline in a second slot of the data unit, said pipelines being arranged to output data for storing in said me

The invention claimed is: 1. A computer system having a memory, a data unit comprising a first parallel execution pipeline in a first slot of the data unit and a second parallel execution pipeline in a second slot of the data unit, said pipelines being arranged to output data for storing in said memory, and at least one other execution pipeline being arranged to output access addresses for the data, and a data memory controller arranged to receive data from each of said at least two parallel execution pipelines and form at least one data queue of data awaiting store operations in said memory, said data memory controller having a first input for receiving data from the first parallel execution pipeline, a second input for receiving data from the second parallel execution pipeline, reordering circuitry to enable reordering of data prior to entry on said at least one data queue and to insert data from said first and second inputs onto said at least one data queue in an order different from the order of arrival of data from said parallel execution pipelines at said first and second inputs such that data from the first slot is inserted onto the queue before data from the second slot and at least one address queue, separate from said at least one data queue, holding store addresses for use in storing data in said memory. 2. A computer system according to claim 1 in which write control circuitry is provided to permit transfer of data from said first and second inputs onto said at least one data queue at clocked write cycles. 3. A computer system according to claim 2 in which said write control circuitry permits data to be written onto said at least one data queue from each of said first and second inputs during a same write cycle. 4. A computer system according to claim 1 in which read control circuitry is provided to permit transfer of data from said at least one data queue to said memory at clocked read cycles. 5. A computer system according to claim 1 in which said reordering circuitry comprises delay circuitry connected to said second input and arranged to delay transfer of data from said second input to said at least one data queue if data is still awaited at said first input for earlier insertion in said at least one data queue. 6. A computer system according to claim 5 in which each of said first and second inputs comprises a selector circuit having one selector input connected to receive data from a respective parallel execution pipeline and a selector output connected to latch circuitry, the latch circuitry being connected to memory access circuitry. 7. A computer system according to claim 6 in which said delay circuitry comprises a loop circuit operable to connect an output of the latch circuitry of said second input to a further input of the selector circuit of said second input thereby causing one or more cycles of delay before transfer of data from the latch circuitry to said memory. 8. A computer system according to claim 7 in which by-pass circuitry is provided for each of said first and second inputs to permit data from said first or second inputs to by-pass said at least one data queue and access said memory when said at least one queue is empty. 9. A computer system according to claim 8 in which an output of the selector circuit of said first input is connected to a by-pass circuit and the selector circuit of said second input is connected to provide a further input to the selector circuit of said first input. 10. A computer system according to claim 1 in which said memory forms a plurality of separately addressable regions including X and Y memory regions, separate queues being provided in said data memory controller for data awaiting store operations in said X and Y memory regions. 11. A computer system according to claim 1 in which said at least one data queue is provided in a FIFO device. 12. A computer system according to claim 1 in which said plurality of parallel execution pipelines include at least two parallel execution pipelines for executing arithmetic operations and at least two parallel execution pipelines for executing memory addressing operations. 13. A computer system according to claim 1 in which clock circuitry is provided to maintain a required order of execution of a plurality of instructions which enter said at least two parallel execution pipelines in a same cycle. 14. A method of operating a computer system having a memory, and a data memory controller and a data unit comprising a first parallel execution pipeline in a first slot of the data unit and a second parallel execution pipeline in a second slot of the data unit, wherein the method comprises outputting data from the first and second parallel execution pipelines for storing in the memory and outputting access addresses onto an address queue from at least one other execution pipeline arranged to output access addresses for the data, receiving data from the first parallel execution pipeline at a first input of the data memory controller and receiving data from the second of said at least two parallel execution pipeline at a second input in the data memory controller, and reordering data at said first and second inputs prior to entry on a data queue to insert data onto said data queue in an order different from an arrival of data from said at least two parallel execution pipelines at said first and second inputs such that data from the first slot is inserted onto the data queue before data from the second slot. 15. A method according to claim 14 in which data arriving at said second input is delayed before adding to said data queue if data is still awaited at said first input for earlier insertion in said data queue. 16. A computer system comprising: a memory; a data unit comprising a first parallel execution pipeline in a first slot of the data unit and a second parallel execution pipeline in a second slot of the data unit, said pipelines being arranged to output data for storing in said memory; at least one other execution pipeline being arranged to output access addresses for the data; and a data memory controller arranged to receive data from each of said at least two parallel execution pipelines and from at least one data queue of data awaiting store operations in said memory, said data memory controller comprising: a first input for receiving data from the first parallel execution pipeline; a second input for receiving data from the second parallel execution pipeline; reordering circuitry to enable reordering of data prior to entry on said at least one data queue and to insert data from said first and second inputs onto said at least one data queue in an order different from the order of arrival of data from said parallel execution pipelines at said first and second inputs such that data from the first slot is inserted onto the queue before data from the second slot; and at least one address queue, separate from said at least one data queue, holding store addresses for use in storing data in said memory, wherein the reordering circuitry comprises delay circuitry connected to said second input and arranged to delay transfer of data from said second input to said at least one data queue if data is still awaited at said first input for earlier insertion in said at least one data queue. 17. A computer system according to claim 16 in which each of said first and second inputs comprises a selector circuit having one selector input connected to receive data from a respective parallel execution pipeline and a selector output connected to latch circuitry, the latch circuitry being connected to memory access circuitry. 18. A computer system according to claim 17 in which said delay circuitry comprises a loop circuit operable to connect an output of the latch circuitry of said second input to a further input of the selector circuit of said second input thereby causing one or more cycles of delay before transfer of data from the latch circuitry to said memory. 19. A computer system according to claim 18 in which by-pass circuitry is provided for each of said first and second inputs to permit data from said first or second inputs to by-pass said at least one data queue and access said memory when said at least one queue is empty. 20. A computer system according to claim 19 in which an output of the selector circuit of said first input is connected to a by-pass circuit and the selector circuit of said second input is connected to provide a further input to the selector circuit of said first input.