IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
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출원번호 |
US-0150893
(2002-05-17)
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우선권정보 |
SG-200201263(2002-03-04) |
발명자
/ 주소 |
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출원인 / 주소 |
|
대리인 / 주소 |
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인용정보 |
피인용 횟수 :
15 인용 특허 :
154 |
초록
▼
An interposer includes a substrate, first and second sets of contact pads carried by the substrate, and receptacles formed in a surface of the substrate and exposing contact pads of the second set. The interposer may also include conductive traces carried by the substrate to electrically connect cor
An interposer includes a substrate, first and second sets of contact pads carried by the substrate, and receptacles formed in a surface of the substrate and exposing contact pads of the second set. The interposer may also include conductive traces carried by the substrate to electrically connect corresponding contact pads of the first and second sets. The receptacles are configured to at least partially receive conductive structures, such as solder balls, that are secured to the contact pads of the second set. Thus, the interposer is useful in providing semiconductor device assemblies and packages of reduced height or profile. Such assemblies and packages are also described, as are multi-chip modules including such assemblies or packages. In addition, methods for designing and fabricating the interposer are disclosed, as are methods for forming assemblies, packages, and multi-chip modules that include the interposer.
대표청구항
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What is claimed is: 1. An interposer for use in a semiconductor device assembly or package, comprising: a substantially planar interposer substrate; at least one attach region on a surface of the interposer substrate including at least one conductive structure for contacting a back side of a semic
What is claimed is: 1. An interposer for use in a semiconductor device assembly or package, comprising: a substantially planar interposer substrate; at least one attach region on a surface of the interposer substrate including at least one conductive structure for contacting a back side of a semiconductor die; a plurality of first contact pads proximate to the at least one attach region; a plurality of second contact pads carried by the interposer substrate, each second contact pad corresponding to a first contact pad of the plurality of first contact pads and electrically connected thereto by a conductive trace extending therebetween; contact receptacles formed at least partially through the interposer substrate and in alignment with at least some second contact pads of the plurality of second contact pads; and at least one additional receptacle formed at least partially through the interposer substrate to expose at least a portion of the at least one conductive structure of the at least one attach region. 2. The interposer of claim 1, wherein each of the plurality of first contact pads, the conductive traces, and the plurality of second contact pads is carried upon the same surface of the interposer substrate. 3. The interposer of claim 2, wherein the at least one attach region is located on the same surface as the plurality of first contact pads, the conductive traces, and the plurality of second contact pads. 4. The interposer of claim 1, wherein the plurality of second contact pads is carried upon an opposite surface of the interposer substrate from that in which the plurality of contact receptacles is formed. 5. The interposer of claim 1, wherein the at least one attach region is located on an opposite surface of the interposer substrate from that in which the plurality of contact receptacles is formed. 6. The interposer of claim 1, wherein the at least one attach region is located upon the same surface of the interposer substrate as that in which the plurality of contact receptacles is formed. 7. The interposer of claim 6, further comprising: at least one receptacle formed in the interposer substrate at the at least one attach region. 8. The interposer of claim 7, wherein the plurality of first contact pads is located within the at least one receptacle. 9. The interposer of claim 8, wherein at least portions of the conductive traces are carried within the interposer substrate. 10. The interposer of claim 1, wherein the at least one conductive structures comprises at least one of an electrically conductive structure and a thermally conductive element. 11. The interposer of claim 1, further comprising: at least one third contact pad accessible from a surface of the substantially planar interposer substrate opposite that in which the plurality of contact receptacles is formed. 12. The interposer of claim 11, wherein the at least one third contact pad communicates with at least one of a first contact pad and a second contact pad. 13. A semiconductor device assembly, comprising: an interposer including contact pads recessed relative to a surface thereof; at least one semiconductor device positioned over the interposer, in contact with at least one conductive structure of the interposer, and including bond pads that communicate with corresponding one of the contact pads; and at least one discrete conductive element secured to the at least one conductive structure and at least partially laterally surrounded by the interposer. 14. The semiconductor device assembly of claim 13, wherein the at least one semiconductor device is secured to the same surface as that in which the contact pads are recessed. 15. The semiconductor device assembly of claim 13, wherein the interposer comprises a recess configured to at least partially receive the at least one semiconductor device. 16. The semiconductor device assembly of claim 14, wherein the at least one semiconductor device is secured and electrically connected to the interposer in a flip-chip orientation. 17. The semiconductor device assembly of claim 13, wherein the at least one semiconductor device is secured to an opposite surface from that in which the contact pads are recessed. 18. The semiconductor device assembly of claim 17, wherein the interposer comprises a recess configured to at least partially receive the at least one semiconductor device. 19. The semiconductor device assembly of claim 13, wherein the contact pads are carried upon an opposite surface of the interposer than that in which contact receptacles in which the contact pads are recessed are formed. 20. The semiconductor device assembly of claim assembly of claim 13, wherein the at least one conductive structure comprises at least one of a ground plane and a thermally conductive element on the interposer and in contact with at least a portion of a back side of the at least one semiconductor device and the interposer further includes at least one receptacle exposing the ground plane, the thermally conductive element, or an additional contact pad in communication with the ground plane or the thermally conductive element, the at least one receptacle being formed in the same surface of the interposer as that in which the contact pads are recessed. 21. A method for fabricating an interposer, comprising: providing a substantially planar interposer substrate with a conductive layer on a surface thereof; patterning the conductive layer to form first contact pads, conductive traces extending laterally from the first contact pads, second contact pads opposite at an opposite end of the conductive traces from the first contact pads, and at least one conductive structure configured to contact a back side of a semiconductor device; forming contact receptacles in an opposite surface of the substantially planar interposer substrate from that on which the conductive layer is formed, each receptacle exposing at least a portion of a corresponding second contact pad; and forming at least one additional receptacle in the opposite surface to expose at least a portion of the at least one conductive structure. 22. The method of claim 21, further comprising: forming the conductive layer on the surface of the substantially planar interposer substrate. 23. The method of claim 21, further comprising: forming at least one recess for at least partially receiving at least one semiconductor device in a surface of the substantially planar interposer substrate. 24. The method of claim 23, wherein forming the at least one recess is effected in the same surface as that upon which the conductive layer is formed. 25. The method of claim 23, wherein forming the at least one recess is effected in a different surface than that upon which the conductive layer is formed. 26. A method for designing an interposer, comprising: configuring a substantially planar interposer substrate; configuring at least one attach location on a surface of the substantially planar interposer substrate; configuring first contact pad locations to be carried by the substantially planar interposer substrate; configuring conductive trace locations to be carried by the substantially planar interposer substrate; configuring second contact pad locations to be carried by the substantially planar interposer substrate, each second contact pad location being configured to be offset from a corresponding first contact pad location, each conductive trace location being configured to extend between the first second corresponding contact pad locations; configuring at least one conductive structure to be carried at least partially by the at least one attach location; configuring contact receptacles to be formed in the substantially planar interposer substrate, a least some of the contact receptacles being configured to at least partially expose corresponding second contact pad locations; and configuring at least one additional receptacle to be formed in the substantially planar interposer substrate to expose at least a portion of the at least one conductive structure. 27. The method of claim 26, wherein configuring the at least one attach location comprises configuring the at least one attach location on the same surface of the substantially planar substrate as that in which the contact receptacles are configured. 28. The method of claim 26, wherein configuring the at least one attach location comprises configuring the at least one attach location in an opposite surface of the substantially planar substrate from that in which the receptacles are configured. 29. The method of claim 26, wherein configuring the at least one conductive structure comprises configuring at least one thermally conductive element location at least partially within the at least one attach location. 30. The method of claim 29, wherein configuring the at least one additional receptacle comprises configuring at least one receptacle to expose at least one of the at least one theramlly conductive element location and a location of an additional contact configured to communicate with the at least one thermally conductive element. 31. The method of claim 26, wherein configuring the at least one conductive structure comprises configuring at least one ground plane location at least partially within the at least one attach location. 32. The method of claim 31, wherein configuring the at least one additional receptacle comprises configuring at least one receptacle to expose at least one of the at least one ground plane location and a location of an additional contact configured to communicate with the at least one ground plane. 33. A method for forming a semiconductor device assembly, comprising: providing an interposer with recessed contact pads; securing at least one semiconductor device to an attach location of the interposer, a back side of the at least one semiconductor device contacting a conductive structure carried at least partially by the attach location; electrically connecting at least one semiconductor device with the interposer; and securing at least one discrete conductive element to the conductive structure, the at least one discrete conductive element being at least partially laterally surrounded by the interposer. 34. The method of claim 33, wherein electrically connecting comprises securing the at least one semiconductor device to the same surface of the interposer as that in which the contact pads are recessed. 35. The method of claim 33, wherein electrically connecting comprises securing the at least one semiconductor device to an opposite surface of the interposer as that in which the contact pads are recessed. 36. The method of claim 33, further comprising: at least partially encapsulating at least the at least one semiconductor device.
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