초록 ▼

A circuit to suppress arc across contacts of a relay is provided, in which the relay is electrically coupled to a power supply and a load. The circuit includes an arc suppression circuit electrically coupled between the first and second contacts of the relay, and the arc suppression circuit includes

A circuit to suppress arc across contacts of a relay is provided, in which the relay is electrically coupled to a power supply and a load. The circuit includes an arc suppression circuit electrically coupled between the first and second contacts of the relay, and the arc suppression circuit includes a capacitor and a switch, both of which are electrically coupled to the first and second contacts of the relay, in which the switch is configured to turn on when the first and second contacts of the relay change state, thereby providing an alternate path for a current flow through the load.

대표청구항 ▼

What is claimed is: 1. A circuit to suppress arc across first and second contacts of a relay, the relay being electrically coupled to a power supply and an inductive load, the circuit comprising: an arc suppression circuit coupled between the first and second contacts of the relay, the arc suppress

What is claimed is: 1. A circuit to suppress arc across first and second contacts of a relay, the relay being electrically coupled to a power supply and an inductive load, the circuit comprising: an arc suppression circuit coupled between the first and second contacts of the relay, the arc suppression circuit including a first capacitor and an FET switch, the FET switch having a drain terminal and a source terminal each electrically coupled to a respective one of the first and second contacts of the relay, the first capacitor being coupled to one contact of the relay and to the FET switch; and a variable charge voltage circuit configured to vary a rate at which the first capacitor charges in accordance with the current flowing through the inductive load, wherein the switch is configured to turn on when the first and second contacts of the relay are opened, thereby providing an alternate path for a current flow through the inductive load. 2. The circuit according to claim 1, wherein the FET switch includes a gate, a drain, and a source, the FET switch being electrically coupled between the first and second contacts of the relay, the first capacitor being electrically coupled to the drain of the FET switch, the arc suppression circuit further including a first resistor electrically coupled between the first capacitor and the gate of the FET switch, a second resistor electrically coupled between the gate of the FET switch and the source of the FET switch, and a diode electrically coupled between the gate of the FET switch and the source of the FET switch. 3. The circuit according to claim 2, wherein the arc suppression circuit further includes a reverse battery protection circuit. 4. The circuit according to claim 3, wherein the reverse battery protection circuit includes a third resistor and a second diode, both of which are electrically coupled between one of the first and second contacts of the relay and the source of the FET switch. 5. A circuit to suppress arc across first and second contacts of a relay, the relay being electrically coupled to a power supply and an inductive load, the circuit comprising: an arc suppression circuit coupled between the first and second contacts of the relay, the arc suppression circuit including a first capacitor and an FET switch, wherein the switch is configured to turn on when the first and second contacts of the relay are opened, thereby providing an alternate path for a current flow through the inductive load; wherein the FET switch includes a gate, a drain, and a source, the FET switch being electrically coupled between the first and second contacts of the relay, the first capacitor being electrically coupled to the drain of the FET switch, the arc suppression circuit further including a first resistor electrically coupled between the first capacitor and the gate of the FET switch, a second resistor electrically coupled between the gate of the FET switch and the source of the FET switch, and a diode electrically coupled between the gate of the FET switch and the source of the FET switch; wherein the arc suppression circuit further includes a variable charge voltage circuit configured to vary a rate at which the first capacitor charges in accordance with the current flowing through inductive load. 6. The circuit according to claim 5, wherein the variable charge voltage circuit includes a third diode electrically coupled to the gate of the FET switch, a fourth resistor electrically coupled to the source of the FET switch, a transistor electrically coupled to the fourth resistor via a base node, a fifth resistor electrically coupled between a collector node of the transistor and the third diode, a sixth resistor electrically coupled between an emitter node of the transistor and the second diode, a seventh resistor electrically coupled between the base node of the transistor and the second diode, and a second capacitor electrically coupled between the base node of the transistor and the second diode. 7. The circuit according to claim 6, wherein the arc suppression circuit further includes a reverse battery protection circuit. 8. The circuit according to claim 7, wherein the reverse battery protection circuit includes a third resistor and a second diode, both of which are electrically coupled between one of the first and second contacts of the relay and the source of the FET switch. 9. A circuit to suppress arc across first and second contacts of a relay, the relay being electrically coupled to a power supply and a load, the circuit comprising: an arc suppression circuit coupled between the first and second contacts of the relay, the arc suppression circuit including a first capacitor and an FET switch, the FET switch having a drain terminal and a source terminal each electrically coupled to a respective one of the first and second contacts of the relay, the capacitor being coupled to one contact of the relay and to the switch; and a variable charge voltage circuit configured to vary a rate at which the first capacitor charges in accordance with the current flowing through the load, wherein the switch is configured to turn on when the first and second contacts of the relay change state, thereby providing an alternate path for a current flow through the load. 10. The circuit according to claim 9, wherein the FET switch includes a gate, a drain, and a source, the FET switch being electrically coupled between the first and second contacts of the relay, the first capacitor being electrically coupled to the drain of the FET switch, the arc suppression circuit further including a first resistor electrically coupled between the first capacitor and the gate of the FET switch, a second resistor electrically coupled between the gate of the FET switch and the source of the FET switch, and a diode electrically coupled between the gate of the FET switch and the source of the FET switch. 11. The circuit according to claim 10, wherein the arc suppression circuit further includes a reverse battery protection circuit. 12. The circuit according to claim 11, wherein the reverse battery protection circuit includes a third resistor and a second diode, both of which are electrically coupled between one of the first and second contacts of the relay and the source of the FET switch. 13. A circuit to suppress arc across first and second contacts of a relay, the relay being electrically coupled to a power supply and a load, the circuit comprising: an arc suppression circuit coupled between the first and second contacts of the relay, the arc suppression circuit including a first capacitor and an FET switch, wherein the switch is configured to turn on when the first and second contacts of the relay change state, thereby providing an alternate path for a current flow through the load; wherein the FET switch includes a gate, a drain, and a source, the FET switch being electrically coupled between the first and second contacts of the relay, the first capacitor being electrically coupled to the drain of the FET switch, the arc suppression circuit further including a first resistor electrically coupled between the first capacitor and the gate of the FET switch, a second resistor electrically coupled between the gate of the FET switch and the source of the FET switch, and a diode electrically coupled between the gate of the FET switch and the source of the FET switch; wherein the arc suppression circuit further includes a variable charge voltage circuit configured to vary a rate at which the first capacitor charges in accordance with the current flowing through load. 14. The circuit according to claim 13, wherein the variable charge voltage circuit includes a third diode electrically coupled to the gate of the FET switch, a fourth resistor electrically coupled to the source of the FET switch, a transistor electrically coupled to the fourth resistor via a base node, a fifth resistor electrically coupled between a collector node of the transistor and the third diode, a sixth resistor electrically coupled between an emitter node of the transistor and the second diode, a seventh resistor electrically coupled between the base node of the transistor and the second diode, and a second capacitor electrically coupled between the base node of the transistor and the second diode. 15. The circuit according to claim 14, wherein the arc suppression circuit further includes a reverse battery protection circuit. 16. The circuit according to claim 15, wherein the reverse battery protection circuit includes a third resistor and a second diode, both of which are electrically coupled between one of the first and second contacts of the relay and the source of the FET switch. 17. The circuit according to claim 2, wherein the first and second resistors are connected in series forming a voltage divider between the first capacitor and the source of the FET switch, a junction point between the first and second resistors being connected to the gate of the FET switch, and said diode being connected between said junction point and said source. 18. The circuit according to claim 10, wherein the first and second resistors are connected in series forming a voltage divider between the first capacitor and the source of the FET switch, a junction point between the first and second resistors being connected to the gate of the FET switch, and said diode being connected between said junction point and said source.