초록 ▼

A storage controller configured to adopt orphaned I/O ports is disclosed. The controller includes multiple field-replaceable units (FRUs) that plug into a backplane having local buses. At least two of the FRUs have microprocessors and memory for processing I/O requests received from host computers f

A storage controller configured to adopt orphaned I/O ports is disclosed. The controller includes multiple field-replaceable units (FRUs) that plug into a backplane having local buses. At least two of the FRUs have microprocessors and memory for processing I/O requests received from host computers for accessing storage devices controlled by the controller. Other of the FRUs include I/O ports for receiving the requests from the hosts and bus bridges for bridging the I/O ports to the backplane local buses in such a manner that if one of the processing FRUs fails, the surviving processing FRU detects the failure and responsively adopts the I/O ports previously serviced by the failed FRU to service the subsequently received I/O requests on the adopted I/O ports. The I/O port FRUs also include I/O ports for transferring data with the storage devices that are also adopted by the surviving processing FRU.

대표청구항 ▼

We claim: 1. A storage controller, for providing fault-tolerant access to storage devices for host computers, comprising: a backplane; a first hot-pluggable field-replaceable unit (FRU), coupled to said backplane and having an input/output (I/O) port configured to receive from the host computers I/

We claim: 1. A storage controller, for providing fault-tolerant access to storage devices for host computers, comprising: a backplane; a first hot-pluggable field-replaceable unit (FRU), coupled to said backplane and having an input/output (I/O) port configured to receive from the host computers I/O requests to access the storage devices; and second and third hot-pluggable FRUs, each coupled to said backplane and having a microprocessor, wherein said second FRU is initially configured to process said I/O requests received by said I/O port, wherein said third FRU is configured to detect that said second FRU has failed and in response to process said I/O requests subsequently received by said I/O port, wherein said third FRU processes said I/O requests subsequently received by said I/O port in response to detecting that said second FRU has failed only if said third FRU microprocessor previously received user input specifying same. 2. The storage controller of claim 1, further comprising: a heartbeat signal, provided by said second FRU to said third FRU, wherein said third FRU detects that said second FRU has failed if said heartbeat signal provided by said second FRU stops. 3. The storage controller of claim 2, wherein said heartbeat signal is comprised in said backplane. 4. The storage controller of claim 1, further comprising: a disable signal, generated by said third FRU to said second FRU, wherein said third FRU disables said second FRU in response to detecting that said second FRU has failed. 5. The storage controller of claim 4, wherein said disable signal is comprised in said backplane. 6. The storage controller of claim 1, wherein said second FRU is configured to initially program said I/O port with a first unique ID for communicating with the host computers. 7. The storage controller of claim 6, wherein said third FRU is further configured to reset said I/O port in response to detecting that said second FRU has failed, and to subsequently program said I/O port with said first unique ID for communicating with the host computers after disabling said second FRU from processing said second I/O requests. 8. The storage controller of claim 1, further comprising: a chassis, for enclosing said backplane and said first, second, and third hot-pluggable FRUs. 9. The storage controller of claim 1, wherein said I/O port is further configured to generate interrupt requests in response to receiving said I/O requests to access the storage devices, wherein said first FRU further comprises: an interrupt router, coupled to receive said interrupt requests from said I/O port, initially configured to route said I/O port interrupt requests to said second FRU; wherein said third FRU is further configured to program said interrupt router to re-route said I/O port interrupt requests to said third FRU rather than to said second FRU in response to detecting that said second FRU has failed. 10. The storage controller of claim 9, wherein said interrupt router comprises a programmable logic device. 11. The storage controller of claim 9, wherein said interrupt router comprises a local bus bridge. 12. The storage controller of claim 1, wherein said I/O port comprises a FibreChannel port. 13. The storage controller of claim 1, wherein said I/O port comprises an Internet SCSI (iSCSI) port. 14. The storage controller of claim 1, wherein said I/O port comprises an Ethernet port. 15. The storage controller of claim 1, wherein said I/O port comprises an Infiniband port. 16. The storage controller of claim 1, wherein said backplane comprises at least first and second local buses coupled to said second and third FRUs, respectively, wherein said first FRU further comprises: a third local bus, coupled to said I/O port; and a bus bridge, for bridging said third local bus to each of said at least first and second local buses. 17. The storage controller of claim 16, wherein said second FRU is initially configured to receive said I/O requests from said I/O port via said first and third local buses, wherein said third FRU is configured to detect that said second FRU has failed and in response to receive said subsequent I/O requests from said I/O port via said second and third local buses. 18. The storage controller of claim 17, wherein said third FRU is configured to program said I/O port via said second and third local buses to transfer data to the host computers from a memory comprised in said third FRU in response to detecting that said second FRU has failed. 19. The storage controller of claim 16, wherein said local buses comprise PCI-X local buses. 20. The storage controller of claim 16, wherein said local buses comprise PCI-Express local buses. 21. The storage controller of claim 16, wherein said local buses comprise PCI local buses. 22. The storage controller of claim 1, wherein said first FRU comprises a plurality of I/O ports each configured to receive from the host computers I/O requests to access the storage devices. 23. The storage controller of claim 22, wherein said third FRU is configured to initially program said plurality of I/O ports with at least one unique ID for communicating with the host computers. 24. The storage controller of claim 23, wherein said third FRU is further configured to reset said plurality of I/O ports in response to detecting that said second FRU has failed, and to subsequently program said plurality of I/O ports with said at least one unique ID for communicating with the host computers after disabling said second FRU from processing said I/O requests. 25. The storage controller of claim 1, wherein said first FRU comprises a second I/O port for communicating with the storage devices, wherein said second FRU is initially configured to process said I/O requests by commanding said second I/O port to transfer data with the storage devices, wherein said third FRU is configured to process said I/O requests subsequently received by said first I/O port by commanding said second I/O port to transfer data with the storage devices in response to detecting that said second FRU has failed. 26. The storage controller of claim 1, wherein the storage controller comprises a fault-tolerant redundant array of inexpensive disks (RAID) controller. 27. The storage controller of claim 1, wherein said microprocessor processing said I/O requests to access the storage devices comprises managing data flow between the storage devices and the host computers. 28. The storage controller of claim 1, wherein said microprocessor processing said I/O requests to access the storage devices comprises performing RAID functions. 29. The storage controller of claim 1, wherein said microprocessor processing said I/O requests to access the storage devices comprises performing translation of logical block locations specified in said I/O requests to logical block locations of the storage devices. 30. The storage controller of claim 1, wherein each of said second and third FRUs further comprises: a memory, coupled to said microprocessor, for caching data read from the storage devices; wherein said microprocessor processing said I/O requests to access the storage devices comprises performing caching of said data read from the storage devices. 31. The storage controller of claim 1, wherein each of said second and third FRUs further comprises: a memory, coupled to said microprocessor, for buffering data transferred between the storage devices and the storage controller; wherein said microprocessor processing said I/O requests to access the storage devices comprises managing said memory for buffering said data transferred between the storage devices and the storage controller. 32. The storage controller of claim 1, wherein said backplane comprises a passive backplane. 33. The storage controller of claim 1, wherein said I/O port is coupled to a network, wherein said I/O port is configured to receive said I/O requests from the host computers via said network. 34. A storage controller, for providing fault-tolerant access to storage devices for host computers, comprising: a backplane; first and second hot-pluggable field-replaceable units (FRUs), each coupled to said backplane and each having an input/output (I/O) port configured to receive from the host computers respective first and second I/O requests to access the storage devices; and third and fourth hot-pluggable FRUs, each coupled to said backplane and having a microprocessor, wherein said third FRU is initially configured to process said first I/O requests to access the storage devices received by said first FRU I/O port, wherein said fourth FRU is initially configured to process said second I/O requests received by said second FRU I/O port, wherein said third FRU is configured to detect that said fourth FRU has failed and in response to process both said first and second I/O requests subsequently received by said first and second FRU I/O ports, wherein said fourth FRU is configured to detect that said third FRU has failed and in response to process both said first and second I/O requests subsequently received by said first and second FRU I/O ports, wherein said third FRU processes both said first and second I/O requests subsequently received by said first and second FRU I/O ports in response to detecting that said fourth FRU has failed only if said third FRU microprocessor previously received user input specifying same, wherein said fourth FRU processes both said first and second I/O requests subsequently received by said first and second FRU I/O ports in response to detecting that said third FRU has failed only if said fourth FRU microprocessor previously received user input specifying same. 35. The storage controller of claim 34, further comprising: a heartbeat signal, provided by each of said third and fourth FRUs to the other of said third and fourth FRUs, wherein said third FRU detects that said fourth FRU has failed if said heartbeat signal provided by said fourth FRU stops, wherein said fourth FRU detects that said third FRU has failed if said heartbeat signal provided by said third FRU stops. 36. The storage controller of claim 35, wherein said heartbeat signals are comprised in said backplane. 37. The storage controller of claim 34, further comprising: a disable signal, generated by each of said third and fourth FRUs to the other of said third and fourth FRUs, wherein said third FRU disables said fourth FRU in response to detecting that said fourth FRU has failed, wherein said fourth FRU disables said third FRU in response to detecting that said third FRU has failed. 38. The storage controller of claim 37, wherein said disable signals are comprised in said backplane. 39. The storage controller of claim 34, wherein said third FRU is configured to initially program said first FRU I/O port with a first unique ID for communicating with the host computers, wherein said fourth FRU is configured to initially program said second FRU I/O port with a second unique ID for communicating with the host computers. 40. The storage controller of claim 39, wherein said third FRU is further configured to reset said second FRU I/O port in response to detecting that said fourth FRU has failed, and to subsequently program said second FRU I/O port with said second unique ID for communicating with the host computers after disabling said fourth FRU from processing said second I/O requests, wherein said fourth FRU is further configured to reset said first FRU I/O port in response to detecting that said third FRU has failed, and to subsequently program said first FRU I/O port with said first unique ID for communicating with the host computers after disabling said third FRU from processing said first I/O requests. 41. The storage controller of claim 34, further comprising: a chassis, for enclosing said backplane and said first, second, third, and fourth hot-pluggable FRUs. 42. The storage controller of claim 34, wherein each of said I/O ports is further configured to generate interrupt requests in response to receiving said respective first and second I/O requests, wherein each of said first and second FRUs further comprises: an interrupt router, coupled to receive said interrupt requests from said I/O port; wherein said first FRU interrupt router is initially configured to route said first FRU I/O port interrupt requests to said third FRU, and said second FRU interrupt router is initially configured to route said second FRU I/O port interrupt requests to said fourth FRU; wherein said third FRU is further configured to program said interrupt router to re-route said second FRU I/O port interrupt requests to said third FRU rather than to said fourth FRU in response to detecting that said fourth FRU has failed, wherein said fourth FRU is further configured to program said interrupt router to re-route said first FRU I/O port interrupt requests to said fourth FRU rather than to said third FRU in response to detecting that said third FRU has failed. 43. The storage controller of claim 42, wherein each of said interrupt routers comprises a programmable logic device. 44. The storage controller of claim 42, wherein each of said interrupt routers comprises a local bus bridge. 45. The storage controller of claim 34, wherein said I/O ports comprise FibreChannel ports. 46. The storage controller of claim 34, wherein said I/O ports comprise Internet SCSI (iSCSI) ports. 47. The storage controller of claim 34, wherein said I/O ports comprise Ethernet ports. 48. The storage controller of claim 34, wherein said I/O ports comprise Infiniband ports. 49. The storage controller of claim 34, wherein said backplane comprises at least first and second local buses coupled to said third FRU and at least third and fourth local buses coupled to said fourth FRU; wherein said first FRU further comprises: a fifth local bus, coupled to said I/O port; and a bus bridge, for bridging said fifth local bus to each of said first and third local buses; wherein said second FRU further comprises: a sixth local bus, coupled to said I/O port; and a bus bridge, for bridging said sixth local bus to each of said second and fourth local buses. 50. The storage controller of claim 49, wherein said third FRU is initially configured to receive said first I/O requests from said first FRU I/O port via said first and fifth local buses, wherein said third FRU is configured to detect that said fourth FRU has failed and in response to additionally receive said subsequent second I/O requests from said second FRU I/O port via said second and sixth local buses, wherein said fourth FRU is initially configured to receive said second I/O requests from said second FRU I/O port via said fourth and sixth local buses, wherein said fourth FRU is configured to detect that said third FRU has failed and in response to additionally receive said subsequent first I/O requests from said first FRU I/O port via said third and fifth local buses. 51. The storage controller of claim 49, wherein said local buses comprise PCI-X local buses. 52. The storage controller of claim 49, wherein said local buses comprise PCI-Express local buses. 53. The storage controller of claim 49, wherein said local buses comprise PCI local buses. 54. The storage controller of claim 34, wherein each of said first and second FRUs comprises a plurality of I/O ports each configured to receive from the host computers a respective first and second plurality of I/O requests to access the storage devices. 55. The storage controller of claim 54, wherein said third FRU is configured to initially program said first FRU plurality of I/O ports with a first plurality of unique IDs for communicating with the host computers, wherein said fourth FRU is configured to initially program said second FRU plurality of I/O ports with a second plurality of unique IDs for communicating with the host computers. 56. The storage controller of claim 55, wherein said third FRU is further configured to reset said second FRU plurality of I/O ports in response to detecting that said fourth FRU has failed, and to subsequently program said second FRU plurality of I/O ports with said second plurality of unique IDs for communicating with the host computers after disabling said fourth FRU from processing said second plurality of I/O requests, wherein said fourth FRU is further configured to reset said first FRU plurality of I/O ports in response to detecting that said third FRU has failed, and to subsequently program said first FRU plurality of I/O ports with said first plurality of unique IDs for communicating with the host computers after disabling said third FRU from processing said first plurality of I/O requests. 57. The storage controller of claim 34, wherein each of said first and second FRUs comprises a second I/O port for communicating with the storage devices, wherein said third FRU is initially configured to process said first I/O requests by commanding said first FRU second I/O port to transfer data with the storage devices, wherein said fourth FRU is initially configured to process said second I/O requests by commanding said second FRU second I/O port to transfer data with the storage devices, wherein said third FRU is configured to process both said first and second I/O requests subsequently received by said first and second FRUs by both commanding said first FRU second I/O port to transfer data with the storage devices and commanding said second FRU second I/O port to transfer data with the storage devices in response to detecting that said fourth FRU has failed, wherein said fourth FRU is configured to process both said first and second I/O requests subsequently received by said first and second FRUs by both commanding said first FRU second I/O port to transfer data with the storage devices and commanding said second FRU second I/O port to transfer data with the storage devices in response to detecting that said third FRU has failed. 58. The storage controller of claim 34, wherein the storage controller comprises a fault-tolerant redundant array of inexpensive disks (RAID) controller. 59. The storage controller of claim 34, wherein said microprocessor processing said I/O requests to access the storage devices comprises managing data flow between the storage devices and the host computers. 60. The storage controller of claim 34, wherein said microprocessor processing said I/O requests to access the storage devices comprises performing RAID functions. 61. The storage controller of claim 34, wherein said microprocessor processing said I/O requests to access the storage devices comprises performing translation of logical block locations specified in said I/O requests to logical block locations of the storage devices. 62. The storage controller of claim 34, wherein each of said third and fourth FRUs comprises: a memory, coupled to said microprocessor, for caching data read from the storage devices; wherein said microprocessor processing said I/O requests to access the storage devices comprises performing caching of said data read from the storage devices. 63. The storage controller of claim 34, wherein each of said third and fourth FRUs comprises: a memory, coupled to said microprocessor, for buffering data transferred between the storage devices and the storage controller; wherein said microprocessor processing said I/O requests to access the storage devices comprises managing said memory for buffering said data transferred between the storage devices and the storage controller. 64. The storage controller of claim 34, wherein said backplane comprises a passive backplane. 65. The storage controller of claim 34, wherein said I/O ports are coupled to a network, wherein said I/O ports are configured to receive said I/O requests from the host computers via said network. 66. The storage controller of claim 34, wherein said first and second I/O requests comprise requests to access respective first and second sets of the storage devices. 67. A storage controller, for providing fault-tolerant access to storage devices for host computers, comprising: a backplane, comprising at least first and second local buses; a first field-replaceable unit (FRU), hot-pluggably coupled to said backplane, comprising: first and second input/output (I/O) controllers, coupled to third and fourth local buses, respectively, each having at least one I/O port for receiving from the host computers first and second I/O requests, respectively, to access the storage devices; and a bus bridge, for bridging each of said first and second local buses to each of said third and fourth local buses; and second and third FRUs, hot-pluggably coupled to said first and second local buses, respectively, wherein said second FRU is initially configured to receive said first I/O requests from said first I/O controller via said first and third local buses and to process same, wherein said third FRU is initially configured to receive said second I/O requests from said second I/O controller via said second and fourth local buses and to process same, wherein said second FRU is configured to detect that said third FRU has failed and in response to also receive subsequent said second I/O requests from said second I/O controller via said first and fourth local buses and to process same, wherein said second FRU is configured to receive subsequent said second I/O requests from said second I/O controller via said first and fourth local buses and to process same in response to detecting that said third FRU has failed only if said second FRU previously received user input specifying same. 68. The storage controller of claim 67, wherein each of said first and second I/O controllers comprises an interrupt request output for indicating reception of respective said first and second I/O requests, wherein said bus bridge is initially configured to couple said first I/O controller interrupt request output to said second FRU and to couple said second I/O controller interrupt request output to said third FRU. 69. The storage controller of claim 68, wherein said second FRU is configured to program said bus bridge to couple said second I/O controller interrupt request output to said second FRU in response to detecting that said third FRU has failed. 70. The storage controller of claim 67, wherein said second FRU is configured to disable said third FRU in response to detecting that said third FRU has failed. 71. The storage controller of claim 67, wherein said third FRU is configured to detect that said second FRU has failed and in response to also receive subsequent said first I/O requests from said first I/O controller via said second and third local buses and to process same. 72. The storage controller of claim 71, wherein said third FRU is configured to program said bus bridge to couple said first I/O controller interrupt request output to said third FRU in response to detecting that said second FRU has failed. 73. The storage controller of claim 71, wherein said third FRU is configured to disable said second FRU in response to detecting that said second FRU has failed. 74. The storage controller of claim 67, wherein said backplane further comprises fifth and sixth local buses, wherein said second and third FRUs are hot-pluggably coupled to said fifth and sixth local buses, respectively, wherein the storage controller further comprises: a fourth field-replaceable unit (FRU), hot-pluggably coupled to said backplane, comprising: third and fourth input/output (I/O) controllers, coupled to seventh and eighth local buses, respectively, each having at least one I/O port for receiving from the host computers third and fourth I/O requests, respectively, to access the storage devices; and a bus bridge, for bridging each of said fifth and sixth local buses to each of said seventh and eighth local buses. 75. The storage controller of claim 74, wherein said second FRU is initially configured to receive said third I/O requests from said third I/O controller via said fifth and seventh local buses and to process same, wherein said third FRU is initially configured to receive said fourth I/O requests from said fourth I/O controller via said sixth and eighth local buses and to process same. 76. The storage controller of claim 75, wherein said second FRU is configured to detect that said third FRU has failed and in response to also receive subsequent said fourth I/O requests from said fourth I/O controller via said fifth and eighth local buses and to process same. 77. The storage controller of claim 76, wherein said third FRU is configured to detect that said second FRU has failed and in response to also receive subsequent said third I/O requests from said third I/O controller via said sixth and seventh local buses and to process same. 78. The storage controller of claim 77, wherein each of said first, second, third, and fourth input/output (I/O) controllers each further comprises a second I/O port for transferring data with the storage devices; wherein said second FRU is initially configured to program said first I/O controller second I/O port to transfer data with the storage devices via said first and third local buses and to program said third I/O controller second I/O port to transfer data with the storage devices via said fifth and seventh local buses, wherein said third FRU is initially configured to program said second I/O controller second I/O port to transfer data with the storage devices via said second and fourth local buses and to program said fourth I/O controller second I/O port to transfer data with the storage devices via said sixth and eighth local buses, wherein said second FRU is configured to detect that said third FRU has failed and in response to also program said second I/O controller second I/O port to transfer data with the storage devices via said first and fourth local buses and to program said fourth I/O controller second I/O port to transfer data with the storage devices via said fifth and eighth local buses. 79. The storage controller of claim 78, wherein said third FRU is configured to detect that said second FRU has failed and in response to also program said first I/O controller second I/O port to transfer data with the storage devices via said second and third local buses and to program said third I/O controller second I/O port to transfer data with the storage devices via said sixth and seventh local buses. 80. The storage controller of claim 67, wherein each of said first and second input/output (I/O) controllers each further comprises a second I/O port for transferring data with the storage devices; wherein said second FRU is initially configured to program said first I/O controller second I/O port to transfer data with the storage devices via said first and third local buses, wherein said third FRU is initially configured to program said second I/O controller second I/O port to transfer data with the storage devices via said second and fourth local buses, wherein said second FRU is configured to detect that said third FRU has failed and in response to also program said second I/O controller second I/O port to transfer data with the storage devices via said first and fourth local buses. 81. The storage controller of claim 80, wherein said third FRU is configured to detect that said second FRU has failed and in response to also program said first I/O controller second I/O port to transfer data with the storage devices via said second and third local buses.