IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0307158
(2002-11-29)
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발명자
/ 주소 |
- Cooper,Barnes
- Kobayashi,Grant H.
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출원인 / 주소 |
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인용정보 |
피인용 횟수 :
21 인용 특허 :
37 |
초록
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A power management technique uses system management interrupt (SMI) to manage states of a processor that includes multiple logical processors. When the SMI is generated, the states of logical processors are verified. When all of the logical processors are idle, the physical processor is placed in a
A power management technique uses system management interrupt (SMI) to manage states of a processor that includes multiple logical processors. When the SMI is generated, the states of logical processors are verified. When all of the logical processors are idle, the physical processor is placed in a low power state.
대표청구항
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What is claimed is: 1. A method, comprising: using system management mode (SMM) to place a physical processor into a lower power state, the physical processor including multiple logical processors, the multiple logical processors sharing execution resources within the physical processor, wherein pl
What is claimed is: 1. A method, comprising: using system management mode (SMM) to place a physical processor into a lower power state, the physical processor including multiple logical processors, the multiple logical processors sharing execution resources within the physical processor, wherein placing the physical processor into the lower power state comprises: enabling an system management interrupt (SMI) trap; executing an instruction that generates a SMI to verify states of the logical processors; keeping track of SMI frequency; and when the SMI frequency exceeds an SMI frequency threshold, disabling the SMI trap for a first period of time. 2. The method of claim 1, wherein the instruction that generates the SMI is an input/output (I/O) instruction that accesses a predetermined register. 3. The method of claim 1, wherein the SMI trap is disabled to reduce the SMI frequency. 4. The method of claim 3, wherein the SMI trap is enabled after expiration of the first period of time. 5. The method of claim 1, wherein when the states of all of the logical processors are verified to be idle, the physical processor is placed into the lower power state. 6. The method of claim 5, wherein when the state of a first logical processor is verified to be non-idle, the physical processor remains in a current state. 7. The method of claim 6, wherein when the physical processor includes two logical processors, and when the state of a second logical processor is repeatedly verified to be idle and the state of the first logical processor is repeatedly verified to be non-idle during a same time period, the SMI trap is disabled for a second period of time. 8. The method of claim 7, wherein the SMI trap is disabled to enable the first logical processor to operate without being interfered by the second logical processor during the second period of time. 9. The method of claim 8, wherein after expiration of the second period of time, the SMI trap is enabled. 10. The method of claim 1, after the SMI is generated, further comprises: disabling the SMI trap for a third period of time to enable communication among the logical processors to settle down; generating a timer SMI when the third period of time expires; verifying the states of the logical processors, wherein when the states of all of the logical processors are idle, the physical processor is placed in the lower power state; and enabling the SMI trap. 11. The method of claim 1, further comprising: keeping track of C state entry frequency; and when the C state entry frequency exceeds a C state entry frequency threshold, disabling the SMI trap for a fourth period of time to reduce the C state entry frequency. 12. The method of claim 1, wherein the physical processor is a processor that supports Hyper-Threading Technology (HT). 13. A computer readable storage medium containing executable instructions which, when executed in a processing system, causes the processing system to perform a method comprising: enabling a system management interrupt (SMI) trap to verify states of two or more logical processors in a physical processor; placing the physical processor into a lower power state when the states of the logical processors are verified to be idle; generating a SMI; and when a number of SMI generated exceeds a threshold, disabling the SMI trap. 14. The computer readable storage medium of claim 13, wherein the SMI trap is disabled for a first period of time. 15. The computer readable storage medium of claim 13, wherein the physical processor includes a first logical processor and a second logical processor, and when the state of the first logical processor is repeatedly verified to be idle and the state of the second logical processor is repeatedly verified to be non-idle, the SMI trap is disabled for a second period of time to enable the first logical processor to operate without being interrupted by the SMI during the second period of time. 16. The computer readable storage medium of claim 13, further comprising: disabling the SMI trap for a third period of time to enable communication among the logical processors to settle down; and generating a timer SMI when the third period of time expires. 17. The computer readable storage medium of claim 16, after the timer SMI is generated, further comprising: verifying the states of the logical processors; when the logical processors are idle, placing the physical processor into the lower power state; and enabling the SMI trap. 18. The computer readable storage medium of claim 17, wherein placing the physical processor into the lower power state comprises: determining if the physical processor was recently placed in the low power state, and if so, disabling the SMI trap for a fourth period of time to reduce frequency of placing the physical processor into the low power state. 19. A system, comprising: a physical processor, the physical processor includes a first logical processor and a second logical processor, wherein the state of the physical processor is managed by generating a system management interrupt (SMI) to verify states of the first logical processor and the second logical processor, the first and second logical processors sharing execution resources within the physical; and a first timer coupled to the physical processor, wherein the first timer is used to reduce SMI frequency when the SMI frequency exceeds a first predetermined threshold or when a C state entry frequency exceeds a second predetermined threshold. 20. The system of claim 19, wherein when the first logical processor and the second logical processor are verified to be idle, the physical processor is placed into a low power state. 21. The system of claim 19, further comprising a second timer coupled to the physical processor, wherein the second timer is used to allow for inter-processor communication among the logical processors before a next SMI is generated, the second timer is set for a shorter time than the first timer. 22. The system of claim 21, further comprising a third timer coupled to the physical processor, wherein the third timer is used to allow the first logical processor to process a single threaded workload when the second logical processor is idle. 23. The system of claim 22, wherein the third timer delays the SMI to be generated while the second logical processor is idle, and wherein the third timer is set for a longer time than the second timer. 24. A system, comprising: a memory; a physical processor coupled to the memory, the physical processor including a first logical processor and a second logical processor, wherein system management mode (SMM) is used to enable placing the physical processor into a low power state, the first and the second logical processors sharing execution resources within the physical; and a first timer coupled to the physical processor to reduce frequency of entering the SMM, wherein the frequency of entering the SMM is reduced to enable processing of a single threaded workload by the first logical processor when the second logical processor is idle. 25. The system of claim 24, wherein the SMM is used to verify states of the logical processors. 26. The system of claim 25, wherein when the states of the logical processors are verified to be idle, the physical processor is placed into the low power mode. 27. The system of claim 24, wherein the frequency of entering the SMM is reduced when both the first logical processor and the second logical processor are busy. 28. The system of claim 24, further comprising a second timer coupled to the physical processor, the second timer used to delay entering the SMM to allow inter-processor communication between the first logical processor and the second logical processor to settle down. 29. A method, comprising: receiving a first system management interrupt (SMI) associated with a first logical processor; determining if both the first logical processor and a second logical processor are idle, the second logical processor coupled to the first logical processor; when both the first and the second logical processors are determined to be idle, placing a physical processor into a low power state, the physical processor including the first and second logical processors; and setting a long timer to delay receiving a second SMI when both the first logical and second logical processors are determined to be busy. 30. The method of claim 29, further comprising: when the second logical processor is not idle, leaving the physical processor in a current power state. 31. The method of claim 29, further comprising: setting a long timer to delay receiving a second SMI when the physical processor is placed into the low power state too frequently. 32. The method of claim 29, further comprising: setting a short timer to delay receiving a second SMI when inter-processor communication occurs between the first and second logical processors. 33. A computer readable storage medium containing executable instructions which, when executed in a processing system, causes the processing system to perform a method comprising: receiving a first system management interrupt (SMI) when an instruction is processed by a first logical processor or by a second logical processor at a first time, the second logical processor coupled to the first logical processor; determining if both the first logical processor and the second logical processor are idle; when both the first logical processor and the second logical processor are determined to be idle, placing a physical processor into a low power state, the physical processor including the first logical processor and the second logical processor; and disabling a second SMI from being generated using a first timer when the instruction is processed at a second time by the first logical processor or by the second logical processor. 34. The computer readable storage medium of claim 33, further comprising: when at least one of the first logical processor and the second logical is not idle, keeping the physical processor in a current power state. 35. The computer readable storage medium of claim 33, wherein the second SMI is disabled from being generated to allow for inter-processor communication between the first logical processor and the second logical processor. 36. The computer readable storage medium of claim 33, wherein upon expiration of the first timer, a timer SMI is received. 37. The computer readable storage medium of claim 36, further comprising: disabling the second SMI from being generated using a second timer when both the first logical processor and the second logical processor are determined to be busy. 38. The computer readable storage medium of claim 37, further comprising: disabling the second SMI from being generated using the second timer when the first logical processor is busy and the second logical processor is idle. 39. The computer readable storage medium of claim 38, further comprising: enabling the second SMI to be generated when the second timer expires.
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