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Ultra-modular processor in lattice topology

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
출원번호 US-0224920 (2002-08-21)
발명자 / 주소
  • McNeil,Donald H.
출원인 / 주소
  • McNeil,Donald H.
대리인 / 주소
    Lowe Hauptman & Berner, LLP
인용정보 피인용 횟수 : 20  인용 특허 : 25

초록

A Modular Operating Topology Element (MOTE), within a software-latticed network, implements ultra-concurrent operation of a plurality of such MOTEs, as single miniaturized packages, e.g., Compact Flash, each with a full function processor (CPU), a unique resident operating system, and dedicated appl

대표청구항

What is claimed is: 1. A computing element, comprising: a first storage area operable to receive and store input data and output data, wherein the input data comprises data received from an external host device for peripheral processing; a second storage area comprising an application program havin

이 특허에 인용된 특허 (25)

  1. Carvey Philip P. ; Dally William J. ; Dennison Larry R., Apparatus and methods for connecting modules using remote switching.
  2. Baker Thomas H., Calendar clock circuit for computer workstations.
  3. Shear Victor H. (Bethesda MD), Database usage metering and protection system and method.
  4. Park, Kyu Ho; Choi, Jong Hyuk; Kim, Bong Wan, Distributed computing system using virtual buses and data communication method for the same.
  5. Pechanek Gerald G. ; Larsen Larry D. ; Glossner Clair John ; Vassiliaadis Stamatis,NLX, Distributed processing array with component processors performing customized interpretation of instructions.
  6. Jones Michael F. (Nashua NH) Zachai Arthur (Swampscott MA), Encrypted data storage card including smartcard integrated circuit for storing an access password and encryption keys.
  7. Robert Leydier FR, Integrated circuit device made secure by means of additional bus lines.
  8. Oz Oved,ILX ; Intrater Gideon,ILX ; Afek Yachin,ILX, Integrated circuit having CPU core operable for switching between two independent asynchronous clock sources of differe.
  9. Norman, Richard S., Integrated circuit having lithographical cell array interconnections.
  10. Cole James F. (Palo Alto CA) McNamara James H. (Santa Cruz CA), Low-power, standby mode computer.
  11. Garney John I., Mechanism supporting execute in place read only memory applications located on removable computer cards.
  12. Wada Manabu (Nagoya JPX), Memory module using dram and method of refreshing the memory module.
  13. Rick Allen Hamilton, II ; Chetan Mehta ; Maulin Ishwarbhai Patel ; Edward Woodrow Wild, Jr., Method and system for enhancing security access to a data processing system.
  14. Paul John David (Boynton Beach FL) Johnson Robert Duane (Boca Raton FL), Method and system for providing discontiguous drive support.
  15. North, Gregory Allen; Perry, Matthew Richard; Kircher, Brian Christopher, Methods and circuits for securing encached information.
  16. Presler-Marshall Martin J. C., Module configuration systems, methods and computer program products for data processing systems.
  17. Shinohara Takayuki (Itami JPX), PC card and PC card system with dual port ram and switchable rewritable ROM.
  18. Wilson, Jeremy Craig, Processor array and parallel data processing methods.
  19. David A. Gilbert, Programmable dedicated application card.
  20. Kerr, Darren; Key, Kenneth Michael; Wright, Michael L.; Jennings, William E., Programmable processing engine for efficiently processing transient data.
  21. Todd Carper ; David Hemmo FR, Smart card memory management system and method.
  22. Chew Gary,SGX, Smart cards, systems using smart cards and methods of operating said cards in systems.
  23. Edelmann George B. (Wilton CT) Hunter Kevin D. (Redbank NJ) Muller Arno (Westport CT) Schmidt ; Jr. Alfred C. (Wilton CT), System for detecting unaccounted for printing in a value printing system.
  24. Fulghum Patrick W., System for upgrading functionality of a peripheral device utilizing a removable ROM having relocatable object code.
  25. Ginter Karl L. ; Shear Victor H. ; Sibert W. Olin ; Spahn Francis J. ; Van Wie David M., Systems and methods for secure transaction management and electronic rights protection.

이 특허를 인용한 특허 (20)

  1. Stergiou, Stergios; Jain, Jawahar, Annotating binary decision diagrams representing sensor data.
  2. Stergiou, Stergios; Jain, Jawahar; Kimura, Yasunori, Annotating environmental data represented by characteristic functions.
  3. Stergiou, Stergios; Jain, Jawahar, Annotating medical binary decision diagrams with health state information.
  4. Stergiou, Stergios; Jain, Jawahar, Annotating medical data represented by characteristic functions.
  5. Stergiou, Stergios; Jain, Jawahar, Combining medical binary decision diagrams for analysis optimization.
  6. Stergiou, Stergios; Jain, Jawahar, Combining medical binary decision diagrams to determine data correlations.
  7. Stergiou, Stergios; Jain, Jawahar, Comparing boolean functions representing sensor data.
  8. Stergiou, Stergios; Jain, Jawahar, Comparing data samples represented by characteristic functions.
  9. Stergiou, Stergios; Jain, Jawahar, Compression threshold analysis of binary decision diagrams.
  10. Stergiou, Stergios; Jain, Jawahar, Detecting data corruption in medical binary decision diagrams using hashing techniques.
  11. Stergiou, Stergios; Jain, Jawahar; Nakata, Tsuneo, Detecting sensor malfunctions using compression analysis of binary decision diagrams.
  12. Langas, Thomas; Djupdal, Asbjom; Ljosland, Borgar; Dybdahl, Torstein Hernes, Electronic devices.
  13. Langas, Thomas; Djupdal, Asbjorn; Ljosland, Borgar; Dybdahl, Torstein Hernes, Master storage device for controlling slave functions of a host electronic device.
  14. Stergiou, Stergios; Jain, Jawahar, Partitioning medical binary decision diagrams for analysis optimization.
  15. Stergiou, Stergios; Jain, Jawahar, Partitioning medical binary decision diagrams for size optimization.
  16. Stergiou, Stergios; Jain, Jawahar, Querying sensor data stored as binary decision diagrams.
  17. Stergiou, Stergios; Jain, Jawahar, Range queries in binary decision diagrams.
  18. Stergiou, Stergios; Jain, Jawahar, Representing sensor data as binary decision diagrams.
  19. Langas, Thomas; Djupdal, Asbjorn; Ljosland, Borgar; Dybdahl, Torstein Hernes, Storage device having master and slave storage device modes.
  20. Stergiou, Stergios; Jain, Jawahar, Validating sensor data represented by characteristic functions.
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