$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Three-dimensional stacked semiconductor package device with bent and flat leads and method of making same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/02
  • H01L-023/48
  • H01L-023/28
  • H01L-023/495
  • H01L-025/10
출원번호 US-0695564 (2003-10-28)
발명자 / 주소
  • Chiang,Cheng Lien
출원인 / 주소
  • Bridge Semiconductor Corporation
인용정보 피인용 횟수 : 52  인용 특허 : 83

초록

초록이 없습니다.

대표청구항

대표청구항이 없습니다.

이 특허에 인용된 특허 (83)

  1. Chia Chok J. ; Lim Seng-Sooi ; Low Qwai H., Apparatus and method for stackable molded lead frame ball grid array packaging of integrated circuits.
    상세보기
  2. Moshayedi Mark (Orange CA), Apparatus for stacking semiconductor chips.
    상세보기
  3. Warren M. Farnworth ; Derek J. Gochnour ; David R. Hembree, CSP BGA test socket with insert and method.
    상세보기
  4. Yoshii Masayuki (Osaka JPX) Mizumo Yoshiyuki (Osaka JPX) Oku Shunji (Osaka JPX) Kowa Mika (Osaka JPX), Chip mounting substrate having an integral molded projection and conductive pattern.
    상세보기
  5. Hong Sung Hak,KRX ; Moon Jong Tae,KRX ; Park Chang Jun,KRX ; Choi Yoon Hwa,KRX, Chip scale package.
    상세보기
  6. Lee Kyu Jin,KRX ; Jeong Do Soo,KRX ; Choi Wan Gyan,KRX ; Chung Tae Gyeong,KRX, Chip-size package (CSP) using a multi-layer laminated lead frame.
    상세보기
  7. Hashemi Seyed H. (Austin TX) Carey David H. (Austin TX), Combined flat capacitor and tab integrated circuit chip and method.
    상세보기
  8. Fusaroli Marzio (Milan ITX) Ceriati Laura (Sesto S. Giovanni ITX), EPROM semiconductor device erasable with ultraviolet rays and manufacturing process thereof.
    상세보기
  9. Webster, Steven; Arellano, Tony; Hollaway, Roy Dale, Fabrication method for integrally connected image sensor packages having a window support in contact with the window and active area.
    상세보기
  10. Burns Carmen D. (Austin TX), High density lead-on-package fabrication method and apparatus.
    상세보기
  11. Go Tiong C. (El Toro CA), High-density electronic modules－process and product.
    상세보기
  12. Endoh Kunihisa (Kawagoe JPX) Hayakawa Yasumitsu (Urawa JPX), Hybrid circuit device.
    상세보기
  13. Hinrichsmeyer Kurt (Sindelfingen DEX) Straehle Werner (Dettenhausen VT DEX) Kelley ; Jr. Gordon A. (Essex Junction VT) Noth Richard W. (Fairfax VT), Integrated semiconductor chip package.
    상세보기
  14. Kwon Young S. (Inchon-jikal KRX) Ahn Seung H. (Suwon KRX), J-leaded semiconductor package having a plurality of stacked ball grid array packages.
    상세보기
  15. Thomas H. Distefano ; Joseph Fjelstad ; John W. Smith, Laterally situated stress/strain relieving lead for a semiconductor chip package.
    상세보기
  16. Masayuki Watanabe (Yokohama JPX) Toshio Sugano (Kokubunji JPX) Seiichiro Tsukui (Komoro JPX) Takashi Ono (Akita JPX) Yoshiaki Wakashima (Kawasaki JPX), Lead connections means for stacked tab packaged IC chips.
    상세보기
  17. Shin Won Sun,KRX ; Han Byung Joon,KRX ; Yoon Ju Hoon,KRX ; Kwak Sung Bum,KRX ; Han In Gyu,KRX, Lead end grid array semiconductor package.
    상세보기
  18. Song Chi J. (Daejon KRX), Lead frame and semiconductor package with such lead frame.
    상세보기
  19. Chew Chee Hiong,MYX ; Chee Hin Kooi,MYX ; Embong Saat Shukri,MYX, Leadframe, method of manufacturing a leadframe, and method of packaging an electronic component utilizing the leadframe.
    상세보기
  20. Mullen ; III William B. (Boca Raton FL) Urbish Glenn F. (Coral Springs FL) Freyman Bruce J. (Plantation FL), Leadless pad array chip carrier.
    상세보기
  21. Akram Salman ; Kinsman Larry, Low profile semiconductor package.
    상세보기
  22. Bai Jinchuan,TWX ; Tsai Chung-Che,TWX, Low profile semiconductor package and process for making the same.
    상세보기
  23. Yamanaka Hideo,JPX, Manufacturing method for semiconductor unit.
    상세보기
  24. Liu Chao-Zen,TWX, Memory module connector.
    상세보기
  25. Sugai Maureen (Phoenix AZ), Method and apparatus for coupling a semiconductor device with a tester.
    상세보기
  26. Tetaka Masafumi,JPX ; Maki Shinichiro,JPX ; Ohyama Nobuo,JPX ; Orimo Seiichi,JPX ; Sakoda Hideharu,JPX ; Yoneda Yoshiyuki,JPX ; Shigeno Akihiro,JPX ; Yokoyama Ryoichi,JPX ; Fujisaki Fumitoshi,JPX ; F, Method and apparatus for fabricating semiconductor device.
    상세보기
  27. Shimizu Shinya (Yokohama JPX), Method for manufacturing a semiconductor device wherein electrodes on a semiconductor chip are electrically connected to.
    상세보기
  28. Kweon Young Do,KRX ; Kim Kwang Soo,KRX, Method for simultaneously manufacturing chip-scale package using lead frame strip with a plurality of lead frames.
    상세보기
  29. Nelson Bradley H. (Austin TX), Method of assembling stacks of integrated circuit dies.
    상세보기
  30. Smith John W. ; Fjelstad Joseph, Method of encapsulating a microelectronic assembly utilizing a barrier.
    상세보기
  31. Go ; deceased Tiong C. (late of El Toro CA by Jane C. Go ; executor) Minahan Joseph A. (Simi Valley CA) Shanken Stuart N. (Laguna Niguel CA), Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting.
    상세보기
  32. Glenn Thomas P., Method of making an integrated circuit package employing a transparent encapsulant.
    상세보기
  33. DiStefano Thomas H. ; Smith John W. ; Mitchell Craig, Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures.
    상세보기
  34. Akram Salman (Boise ID) Wood Alan G. (Boise ID) Farnworth Warren M. (Nampa ID), Method of producing a single piece package for semiconductor die.
    상세보기
  35. Fjelstad Joseph, Methods for manufacturing a semiconductor package having a sacrificial layer.
    상세보기
  36. Thomas P. Glenn ; Scott J. Jewler ; David Roman ; J. H. Yee KR; D. H. Moon KR, Methods for moding a leadframe in plastic integrated circuit devices.
    상세보기
  37. Washida Tetsuro,JPX ; Ochi Katsunori,JPX, Module mounted with semiconductor device.
    상세보기
  38. Kimura Naoto,JPX, Mold-BGA-type semiconductor device and method for making the same.
    상세보기
  39. Glenn Thomas P., Mounting having an aperture cover with adhesive locking feature for flip chip optical integrated circuit device.
    상세보기
  40. Uchiyama Kenji,JPX, Mounting structure of semiconductor chip, liquid crystal device, and electronic equipment.
    상세보기
  41. Mori Syuji,JPX ; Sekiba Takasi,JPX ; Kudo Osamu,JPX, Multi-chip semiconductor chip module.
    상세보기
  42. Oguchi Satoshi (Ohme JPX) Ishihara Masamichi (Hamura JPX) Ito Kazuya (Hamura JPX) Murakami Gen (Tama JPX) Anjoh Ichiro (Koganei JPX) Sakuta Toshiyuki (Ohme JPX) Yamaguchi Yasunori (Ohme JPX) Kasama Y, Multi-chip semiconductor package.
    상세보기
  43. Miremadi Jian ; Schuyler Marc P., Multiple chip assembly.
    상세보기
  44. Hallenbeck Gary A. (Fairport NY) Janson ; Jr. Wilbert F. (Shortsville NY) Jones William B. (Rochester NY), Optoelectronic device component package.
    상세보기
  45. McMahon John F. ; Mahajan Ravi, Organic substrate (PCB) slip plane "stress deflector" for flip chip deivces.
    상세보기
  46. Glenn Thomas P. ; Jewler Scott J. ; Roman David ; Yee J. H.,KRX ; Moon D. H.,KRX, Plastic integrated circuit device package and leadframe having partially undercut leads and die pad.
    상세보기
  47. Glenn Thomas P., Plastic package for an optical integrated circuit device and method of making.
    상세보기
  48. Kim Jae J. (Seoul KRX) Kim Dong K. (Chunan KRX) Ahn Seung H. (Suwon KRX), Semiconductor assembly for a three-dimensional integrated circuit package.
    상세보기
  49. Ill Heung Choi KR; Young Hee Song KR, Semiconductor chip package.
    상세보기
  50. King Jerrold L. (Boise ID) Brooks Jerry M. (Caldwell ID), Semiconductor chip package.
    상세보기
  51. Kazunari Michii JP, Semiconductor device.
    상세보기
  52. Ouchida Takayuki,JPX, Semiconductor device.
    상세보기
  53. Toshio Miyamoto JP; Asao Nishimura JP; Koki Noguchi JP; Satoshi Michishita JP; Masashi Horiguchi JP; Masaharu Kubo JP; Kazuyoshi Shiba JP, Semiconductor device.
    상세보기
  54. Yamaji Yasuhiro (Kawasaki JPX), Semiconductor device.
    상세보기
  55. Nobuaki Hashimoto JP, Semiconductor device and method of manufacture thereof, circuit board, and electronic instrument.
    상세보기
  56. Tsuji Masahiro (Kyoto JPX), Semiconductor device having a multilayer interconnection structure.
    상세보기
  57. Maekawa Hideaki,JPX, Semiconductor device having an improved structure for storing a semiconductor chip.
    상세보기
  58. McShane Michael B. (Austin TX) Lin Paul T. (Austin TX), Semiconductor device having dual electrical contact sites.
    상세보기
  59. Okumura Katsuya (Yokohama JPX), Semiconductor device having stacking structure.
    상세보기
  60. Kuraishi Fumio,JPX ; Yumoto Kazuhito,JPX ; Hayashi Mamoru,JPX, Semiconductor device having tab tape lead frame with reinforced outer leads.
    상세보기
  61. Tsuji Kazuto,JPX ; Yoneda Yoshiyuki,JPX ; Sakoda Hideharu,JPX ; Nomoto Ryuuji,JPX ; Watanabe Eiji,JPX ; Orimo Seiichi,JPX ; Onodera Masanori,JPX ; Kasai Junichi,JPX, Semiconductor device including a frame terminal.
    상세보기
  62. Nakamura Tetsuro (Takarazuka JPX) Tanaka Eiichiro (Osaka JPX) Fujiwara Shinji (Kobe JPX) Nakagawa Masahiro (Osaka JPX), Semiconductor device, an image sensor device, and methods for producing the same.
    상세보기
  63. Watanabe Masayuki,JPX ; Sugano Toshio,JPX ; Tsukui Seiichiro,JPX ; Ono Takashi,JPX ; Wakashima Yoshiaki,JPX, Semiconductor memory module having double-sided stacked memory chip layout.
    상세보기
  64. Takahashi Yoshiharu (Itami JPX) Hirose Tetsuya (Itami JPX) Ichiyama Hideyuki (Itami JPX), Semiconductor pressure sensor.
    상세보기
  65. Clements Ken (Santa Cruz CA), Semiconductor wafer array.
    상세보기
  66. Clements Ken (Santa Cruz CA), Semiconductor wafer array with electrically conductive compliant material.
    상세보기
  67. Farnworth Warren M. ; King Jerrold L., Single-piece molded module housing.
    상세보기
  68. Degani Yinon ; Tai King Lien, Solder bonding printed circuit boards.
    상세보기
  69. Hatada Kenzo (Katano JPX), Stack type semiconductor package.
    상세보기
  70. Corisis David J. ; Brooks Jerry M. ; Moden Walter L., Stackable ball grid array package.
    상세보기
  71. Bellaar Pieter H.,NLX, Stacked chip assembly.
    상세보기
  72. An Min Cheol,KRX ; Jeong Do Soo,KRX, Stacked chip package device employing a plurality of lead on chip type semiconductor chips.
    상세보기
  73. Chia-Yu Hung TW, Stacked integrated circuit structure.
    상세보기
  74. Akram Salman, Stacked leads-over-chip multi-chip module.
    상세보기
  75. Choi Chang Kuk,KRX, Stacked package for semiconductor device and fabrication method thereof, and apparatus for making the stacked package.
    상세보기
  76. Kang Kyung Suk,KRX, Stacked package of semiconductor package units via direct connection between leads and stacking method therefor.
    상세보기
  77. Ohuchi Shinji,JPX, Stacked semiconductor device.
    상세보기
  78. Park Jong Y. (Bucheon KRX) Choi Jong K. (Incheon KRX), Surface mount semiconductor package.
    상세보기
  79. Huang Chien-Ping,TWX ; Ko Eric,TWX, Thermally enhanced quad flat non-lead package of semiconductor.
    상세보기
  80. Lee Seon Goo,KRX, Thin, stackable semiconductor packages.
    상세보기
  81. Nakaya Hiroaki (Tenri JPX) Yamashita Takuo (Tenri JPX) Ogura Takashi (Nara JPX) Yoshida Masaru (Ikoma JPX), Thin-film electroluminescence device.
    상세보기
  82. Jeong Do Soo,KRX ; An Min Cheol,KRX ; Ahn Seung Ho,KRX ; Jeong Hyeon Jo,KRX ; Choi Ki Won,KRX, Three dimensional stack package device having exposed coupling lead portions and vertical interconnection elements.
    상세보기
  83. Vindasius Alfons ; Sautter Kenneth M., Vertical interconnect process for silicon segments with thermally conductive epoxy preform.
    상세보기

이 특허를 인용한 특허 (52)

  1. Juengling, Werner, Data cells with drivers and methods of making and operating the same.
    상세보기
  2. Juengling, Werner, Data cells with drivers and methods of making and operating the same.
    상세보기
  3. Juengling, Werner, Data cells with drivers and methods of making and operating the same.
    상세보기
  4. Juengling, Werner, Data cells with drivers and methods of making and operating the same.
    상세보기
  5. Juengling, Werner, Devices including fin transistors robust to gate shorts and methods of making the same.
    상세보기
  6. Juengling, Werner, Devices including fin transistors robust to gate shorts and methods of making the same.
    상세보기
  7. Juengling, Werner, Devices with cavity-defined gates and methods of making the same.
    상세보기
  8. Co, Reynaldo; Leal, Jeffrey S.; Pangrle, Suzette K.; McGrath, Scott; Melcher, De Ann Eileen; Barrie, Keith L.; Villavicencio, Grant; Del Rosario, Elmer M.; Bray, John R., Electrical connector between die pad and z-interconnect for stacked die assemblies.
    상세보기
  9. Co, Reynaldo; Leal, Jeffrey S.; Pangrle, Suzette K.; McGrath, Scott; Melcher, DeAnn Eileen; Barrie, Keith L.; Villavicencio, Grant; del Rosario, Elmer M.; Bray, John R., Electrical connector between die pad and z-interconnect for stacked die assemblies.
    상세보기
  10. Co, Reynaldo; Villavicencio, Grant; Leal, Jeffrey S.; McElrea, Simon J. S., Electrical interconnect for die stacked in zig-zag configuration.
    상세보기
  11. McElrea, Simon J. S.; Andrews, Jr., Lawrence Douglas; McGrath, Scott; Caskey, Terrence; Crane, Scott Jay; Robinson, Marc E.; Cantillep, Loreto, Electrically interconnected stacked die assemblies.
    상세보기
  12. McElrea, Simon J. S.; Andrews, Jr., Lawrence Douglas; McGrath, Scott; Caskey, Terrence; Crane, Scott Jay; Robinson, Marc E.; Cantillep, Loreto, Electrically interconnected stacked die assemblies.
    상세보기
  13. Tao, Min; Sun, Zhuowen; Kim, Hoki; Zohni, Wael; Agrawal, Akash, Enhanced density assembly having microelectronic packages mounted at substantial angle to board.
    상세보기
  14. Kim, Oh Han; Kim, Kyung Moon, Flip chip interconnection system having solder position control mechanism.
    상세보기
  15. Zhang, Xiaotian; Yilmaz, Hamza; Lu, Jun; Zeng, Xiaoguang; Lu, Ming-Chen, Flip chip semiconductor device.
    상세보기
  16. Katkar, Rajesh; Co, Reynaldo; McGrath, Scott; Prabhu, Ashok S.; Lee, Sangil; Wang, Liang; Shen, Hong, Flipped die stack.
    상세보기
  17. Prabhu, Ashok S.; Katkar, Rajesh; Wang, Liang; Uzoh, Cyprian Emeka, Flipped die stack assemblies with leadframe interconnects.
    상세보기
  18. Delacruz, Javier A.; Haba, Belgacem; Vu, Tu Tam; Katkar, Rajesh, Flipped die stacks with multiple rows of leadframe interconnects.
    상세보기
  19. Delacruz, Javier A.; Haba, Belgacem; Vu, Tu Tam; Katkar, Rajesh, Flipped die stacks with multiple rows of leadframe interconnects.
    상세보기
  20. Do, Byung Tai; Shim, Il Kwon; Chow, Seng Guan, Integrated circuit packaging system substrates and method of manufacture thereof.
    상세보기
  21. Kirsch, Howard C.; Ingalls, Charles; Juengling, Werner, Memory structure having volatile and non-volatile memory portions.
    상세보기
  22. Juengling, Werner, Methods of forming data cells and connections to data cells.
    상세보기
  23. Haba, Belgacem; Sun, Zhuowen; Delacruz, Javier A., Microelectronic packages and assemblies with improved flyby signaling operation.
    상세보기
  24. Leal, Jeffrey S., Selective die electrical insulation by additive process.
    상세보기
  25. Leal, Jeffrey S., Selective die electrical insulation by additive process.
    상세보기
  26. Bae, Jin Ho, Semiconductor device and package.
    상세보기
  27. Bae, Jin Ho, Semiconductor device and package.
    상세보기
  28. Co, Reynaldo; Melcher, DeAnn Eileen; Pan, Weiping; Villavicencio, Grant, Semiconductor die array structure.
    상세보기
  29. Crane, Scott Jay; McElrea, Simon J. S.; McGrath, Scott; Pan, Weiping; Melcher, De Ann Eileen; Robinson, Marc E., Semiconductor die mount by conformal die coating.
    상세보기
  30. Crane, Scott Jay; McElrea, Simon J. S.; McGrath, Scott; Pan, Weiping; Melcher, De Ann Eileen; Robinson, Marc E., Semiconductor die mount by conformal die coating.
    상세보기
  31. Crane, Scott Jay; McElrea, Simon J. S.; McGrath, Scott; Pan, Weiping; Melcher, DeAnn Eileen; Robinson, Marc E., Semiconductor die mount by conformal die coating.
    상세보기
  32. Lee, Hun Teak; Kim, Jong Kook; Kim, ChulSik; Jang, Ki Youn, Semiconductor package system with fine pitch lead fingers and method of manufacturing thereof.
    상세보기
  33. Lee, Hun Teak; Kim, Jong Kook; Kim, ChulSik; Jang, Ki Youn, Semiconductor system with fine pitch lead fingers and method of manufacturing thereof.
    상세보기
  34. McGrath, Scott; Leal, Jeffrey S.; Shenoy, Ravi; Cantillep, Loreto; McElrea, Simon; Pangrle, Suzette K., Stacked die assembly having reduced stress electrical interconnects.
    상세보기
  35. McElrea, Simon J. S.; Robinson, Marc E.; Andrews, Jr., Lawrence Douglas, Support mounted electrically interconnected die assembly.
    상세보기
  36. Juengling, Werner, Systems and devices including fin field-effect transistors each having U-shaped semiconductor fin.
    상세보기
  37. Juengling, Werner, Systems and devices including local data lines and methods of using, making, and operating the same.
    상세보기
  38. Juengling, Werner, Systems and devices including multi-gate transistors and methods of using, making, and operating the same.
    상세보기
  39. Juengling, Werner, Systems and devices including multi-gate transistors and methods of using, making, and operating the same.
    상세보기
  40. Juengling, Werner, Systems and devices including multi-gate transistors and methods of using, making, and operating the same.
    상세보기
  41. Juengling, Werner, Systems and devices including multi-gate transistors and methods of using, making, and operating the same.
    상세보기
  42. Juengling, Werner, Systems and devices including multi-transistor cells and methods of using, making, and operating the same.
    상세보기
  43. Juengling, Werner, Systems and devices including multi-transistor cells and methods of using, making, and operating the same.
    상세보기
  44. Juengling, Werner, Transistor with a passive gate.
    상세보기
  45. Caskey, Terrence; Andrews, Jr., Lawrence Douglas; McGrath, Scott; McElrea, Simon J. S.; Du, Yong; Scott, Mark, Vertical electrical interconnect formed on support prior to die mount.
    상세보기
  46. Juengling, Werner, Vertically stacked fin transistors and methods of fabricating and operating the same.
    상세보기
  47. Prabhu, Ashok S.; Katkar, Rajesh; Moran, Sean, Wafer-level flipped die stacks with leadframes or metal foil interconnects.
    상세보기
  48. Prabhu, Ashok S.; Katkar, Rajesh; Moran, Sean, Wafer-level flipped die stacks with leadframes or metal foil interconnects.
    상세보기
  49. Lee, Hun-Teak; Kim, Jong-Kook; Kim, Chul-Sik; Jang, Ki-Youn; Pendse, Rajendra D., Wire bond interconnection.
    상세보기
  50. Lee, Hun-Teak; Kim, Jong-Kook; Kim, Chul-Sik; Jang, Ki-Youn; Pendse, Rajendra D., Wire bond interconnection and method of manufacture thereof.
    상세보기
  51. Pendse, Rajendra D.; Han, Byung Joon; Lee, Hun Teak, Wire bonding structure and method that eliminates special wire bondable finish and reduces bonding pitch on substrates.
    상세보기
  52. Pendse, Rajendra D.; Han, Byung Joon; Lee, HunTeak, Wire bonding structure and method that eliminates special wire bondable finish and reduces bonding pitch on substrates.
    상세보기

관련 콘텐츠

섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로