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Configurable integrated circuit with offset connection 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-025/00
출원번호 US-0882713 (2004-06-30)
발명자 / 주소
  • Rohe,Andre
  • Teig,Steven
출원인 / 주소
  • Rohe,Andre
  • Teig,Steven
대리인 / 주소
    Stattler Johansen & Adeli LLP
인용정보 피인용 횟수 : 23  인용 특허 : 66

초록

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대표청구항

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이 특허에 인용된 특허 (66)

  1. Lo, William, Circuit for reducing pin count of a semiconductor chip and method for configuring the chip.
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  4. Snyder, Warren, Configuring digital functions in a digital configurable macro architecture.
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  5. Scalera Stephen M. ; Vazquez Jose R., Context switchable field programmable gate array with public-private addressable sharing of intermediate data.
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  6. Iadanza Joseph A., Cross-coupled bitline segments for generalized data propagation.
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  7. Or-Bach, Zvi; Wurman, Ze'ev; Zeman, Richard; Cooke, Laurance, Customizable and programmable cell array.
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  8. Altaf, K. Risa, Driver circuitry for programmable logic devices with hierarchical interconnection resources.
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  9. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., FPGA configurable logic block with multi-purpose logic/memory circuit.
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  10. James L. Burnham ; Gary R. Lawman ; Joseph D. Linoff, FPGA customizable to accept selected macros.
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  11. Chaudhary Kamal, FPGA having logic element carry chains capable of generating wide XOR functions.
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  12. Carberry, Richard A.; Young, Steven P.; Bauer, Trevor J., FPGA lookup table with speed read decoder.
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  13. Pi, Tao; Crotty, Patrick J., FPGA lookup table with transmission gate structure for reliable low-voltage operation.
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  14. Young Steven P. ; Chaudhary Kamal ; Bauer Trevor J., FPGA repeatable interconnect structure with hierarchical interconnect lines.
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  15. Kean Thomas A.,GB6 ITX EH88JQ ; Wilkie William A.,GB6 ITX EH106AP, FPGA with parallel and serial user interfaces.
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  16. Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray, Field programmable memory array.
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  19. Manabe Yoshio,JPX, Field-programmable gate array with ferroelectric thin film.
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  20. Bennett David Wayne (Louisville CO) Dellinger Eric Ford (Boulder CO) Manaker ; Jr. Walter A. (Boulder CO) Stern Carl M. (Boulder CO) Troxel William R. (Longmont CO) Young Jay Thomas (Louisville CO), Frequency driven layout and method for field programmable gate arrays.
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  21. Southgate Timothy J. ; Wenzler Michael, Graphic editor for block diagram level design of circuits.
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  22. Rostoker Michael D. ; Koford James S. ; Scepanovic Ranko ; Jones Edwin R. ; Padmanahben Gobi R. ; Kapoor Ashok K. ; Kudryavtsev Valeriy B.,RUX ; Andreev Alexander E.,RUX ; Aleshin Stanislav V.,RUX ; , Hexagonal field programmable gate array architecture.
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  23. Laramie Michael J., Interconnect structure between heterogeneous core regions in a programmable array.
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  24. Goetting F. Erich (Cupertino CA) Trimberger Stephen M. (San Jose CA), Logic cell for field programmable gate array having optional internal feedback and optional cascade.
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  25. New Bernard J. (Los Gatos CA), Logic structure and circuit for fast carry.
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  26. Norman Kevin A. ; Patel Rakesh H. ; Sample Stephen P. ; Butts Michael R., Look-up table based logic element with complete permutability of the inputs to the secondary signals.
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  27. Chiang David (Saratoga CA) Lee Napoleon W. (Fremont CA) Ho Thomas Y. (Milpitas CA) Harrison David A. (Cupertino CA) Kucharewski ; Jr. Nicholas (Pleasanton CA) Seltzer Jeffrey H. (San Jose CA), Macrocell with product-term cascade and improved flip flop utilization.
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  28. Clinton Kim P. N. ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Seidel Victor Paul ; Zittritsch Terrance John, Memory cells for field programmable memory array.
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  29. Larsen Wendell Ray (Essex Junction VT) Keyser Frank Ray (Colchester VT) Worth Brian A. (Milton VT), Memory mapping method and apparatus to fold sparsely populated structures into densely populated memory columns or rows.
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  30. Conn ; Jr. Robert O., Method and apparatus for measuring localized voltages on programmable integrated circuits.
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  31. Gould Scott W. (So. Burlington VT), Method and system for enhanced drive in programmmable gate arrays.
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  32. Fuller Christine Marie ; Hartman Steven Paul ; Millham Eric Ernest, Method and system for optimizing a critical path in a field programmable gate array configuration.
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  33. Craft David John ; Gould Scott Whitney ; Keyser ; III Frank Ray ; Worth Brian, Method and system for programming a gate array using a compressed configuration bit stream.
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  34. Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable function within a chip to enable configurable I/O signal timing characteristics.
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  35. Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable function within a standard cell chip for repair of logic circuits.
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  36. Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable interconnect within an ASIC for configuring the ASIC.
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  37. Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of an embedded field programmable gate array interconnect for flexible I/O connectivity.
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  38. Baxter, Glenn A., Method for controlling timing in reduced programmable logic devices.
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  39. Glenn A. Baxter, Method for converting programmable logic devices into standard cell devices.
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  40. Schiefele, Walter P.; Krueger, Robert O., Method for creating circuit redundancy in programmable logic devices.
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  41. Trimberger, Stephen M., Method for making large-scale ASIC using pre-engineered long distance routing structure.
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  42. Baxter, Glenn A., Method for managing database models for reduced programmable logic device components.
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  43. Trimberger Stephen M. (San Jose CA), Method for programming an FPLD using a library-based technology mapping algorithm.
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  44. Trimberger Stephen M. (San Jose CA), Method for programming an FPLD using a library-based technology mapping algorithm.
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  45. Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Zittritsch Terrance John, Method of operating a field programmable memory array with a field programmable gate array.
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  46. Kelem Steven H. ; Lawman Gary R., On-chip logic analysis and method for using the same.
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  47. Chaudhary Kamal ; Nag Sudip K., Post-placement residual overlap removal method for core-based PLD programming process.
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  48. Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Zittritsch Terrance John, Programmable address decoder for field programmable memory array.
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  49. Gould Scott Whitney ; Keyser ; III Frank Ray ; Larsen Wendell Ray ; Worth Brian Allen, Programmable array interconnect latch.
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  50. Clinton Kim P. N. (Essex Junction VT) Gould Scott W. (South Burlington VT) Hartman Steven P. (Jericho VT) Iadanza Joseph A. (Hinesburg VT) Keyser ; III Frank R. (Colchester VT) Millham Eric E. (St. G, Programmable array interconnect network.
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  51. Iadanza Joseph Andrew ; Keyser ; III Frank Ray, Programmable bit line drive modes for memory arrays.
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  52. El Gamal Abbas A. (Palo Alto CA) El-Ayat Khaled A. (Cupertino CA) Greene Jonathan W. (Palo Alto CA) Guo Ta-Pen R. (Cupertino CA) Reyneri Justin M. (Los Altos CA), Programmable interconnect architecture.
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  53. New Bernard J. ; Carberry Richard A., Programmable logic device having configurable logic blocks with user-accessible input multiplexers.
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  54. Baxter, Glenn A., Programmable logic device structures in standard cell devices.
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  55. Iadanza Joseph Andrew, Programmable parity checking and comparison circuit.
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  56. Iadanza Joseph Andrew, Programmable read ports and write ports for I/O buses in a field programmable memory array.
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  57. Darling, Roy D.; Shimanek, Schuyler E.; Davies, Jr., Thomas J., Programming on-the-fly (OTF).
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  58. New Bernard J. ; Johnson Robert Anders ; Wittig Ralph ; Mohan Sundararajarao, Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM.
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  59. Ochotta Emil S. ; Wieland Douglas P., Routing architecture using a direct connect routing mesh.
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  60. Eric R. Keller ; Steven A. Guccione ; Delon Levi, Run-time routing for programmable logic devices.
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  61. Clinton Kim P. N. ; Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Kilmoyer Ralph David ; Laramie Michael Joseph ; Seidel Victor Paul ; Zittritsch Terrance John, Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array.
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  62. Zhou,Shi dong, Structures and methods of implementing a pass gate multiplexer with pseudo-differential input signals.
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  63. Elftmann, Daniel; Speers, Theodore; Kundu, Arunangshu, Synchronous first-in/first-out block memory for a field programmable gate array.
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  64. Iadanza Joseph Andrew (Hinesburg VT), System and method for dynamically reconfiguring a programmable gate array.
    상세보기
  65. Gould Scott Whitney (Burlington VT), System for enhanced drive in programmable gate arrays.
    상세보기
  66. Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Kilmoyer Ralph David ; Laramie Michael Joseph, System for implementing write, initialization, and reset in a memory array using a single cell write port.
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이 특허를 인용한 특허 (23)

  1. Redgrave, Jason; Schmit, Herman, Barrel shifter implemented on a configurable integrated circuit.
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  2. Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu; Redgrave, Jason, Configurable IC with configurable routing resources that have asymmetric input and/or outputs.
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  3. Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu; Redgrave, Jason, Configurable IC with configuration logic resources that have asymmetric inputs and/or outputs.
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  4. Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu, Configurable IC with logic resources with offset connections.
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  5. Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu, Configurable IC with routing circuits with offset connections.
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  6. Schmit,Herman; Teig,Steven; Hutchings,Brad; Huang,Randy Renfu, Configurable IC with routing circuits with offset connections.
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  7. Redgrave, Jason; Schmit, Herman; Teig, Steven; Hutchings, Brad L.; Huang, Randy R., Configurable IC'S with large carry chains.
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  8. Teig, Steven; Redgrave, Jason, Configurable IC's with dual carry chains.
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  9. Schmit, Herman; Redgrave, Jason, Configurable IC's with large carry chains.
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  10. Schmit,Herman; Teig,Steven; Hutchings,Brad; Huang,Randy Renfu, Configurable IC's with logic resources with offset connections.
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  11. Rohe, Andre; Teig, Steven, Configurable integrated circuit with built-in turns.
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  12. Rohe, Andre; Teig, Steven, Configurable integrated circuit with built-in turns.
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  13. Rohe, Andre; Teig, Steven, Configurable integrated circuit with different connection schemes.
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  14. Rohe,Andre; Teig,Steven, Configurable integrated circuit with offset connections.
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  15. Schmit,Herman; Teig,Steven; Hutchings,Brad, Configurable integrated circuit with parallel non-neighboring offset connections.
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  16. Young,Steven P., Integrated circuit with programmable routing structure including diagonal interconnect lines.
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  17. Young,Steven P., Integrated circuit with programmable routing structure including straight and diagonal interconnect lines.
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  18. Rohe, Andre; Teig, Steven, Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit.
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  19. Rohe, Andre; Teig, Steven, Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit.
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  20. Rohe, Andre; Teig, Steven, Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit.
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  21. Rohe,Andre; Teig,Steven, Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit.
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  22. Schmit, Herman; Teig, Steven, Via programmable gate array with offset bit lines.
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  23. Schmit, Herman; Teig, Steven, Via programmable gate array with offset direct connections.
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