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Configurable circuits, IC's, and systems 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/10
  • H01L-029/02
  • H01L-029/40
  • H01L-029/06
  • H01L-029/08
  • H01L-051/00
출원번호 US-0882946 (2004-06-30)
발명자 / 주소
  • Schmit,Herman
  • Butts,Michael
  • Hutchings,Brad L.
  • Teig,Steven
출원인 / 주소
  • Schmit,Herman
  • Butts,Michael
  • Hutchings,Brad L.
  • Teig,Steven
대리인 / 주소
    Stattler Johansen & Adeli LLP
인용정보 피인용 횟수 : 87  인용 특허 : 69

초록

초록이 없습니다.

대표청구항

대표청구항이 없습니다.

이 특허에 인용된 특허 (69)

  1. Lo, William, Circuit for reducing pin count of a semiconductor chip and method for configuring the chip.
    상세보기
  2. Cliff Richard G., Coarse-grained look-up table architecture.
    상세보기
  3. Kaviani Alireza S.,CAXITX M5R 2R5 ; Brown Steven D.,CAXITX M4R 2A3, Computational field programmable architecture.
    상세보기
  4. Snyder, Warren, Configuring digital functions in a digital configurable macro architecture.
    상세보기
  5. Scalera Stephen M. ; Vazquez Jose R., Context switchable field programmable gate array with public-private addressable sharing of intermediate data.
    상세보기
  6. Iadanza Joseph A., Cross-coupled bitline segments for generalized data propagation.
    상세보기
  7. Or-Bach, Zvi; Wurman, Ze'ev; Zeman, Richard; Cooke, Laurance, Customizable and programmable cell array.
    상세보기
  8. Altaf, K. Risa, Driver circuitry for programmable logic devices with hierarchical interconnection resources.
    상세보기
  9. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., FPGA configurable logic block with multi-purpose logic/memory circuit.
    상세보기
  10. James L. Burnham ; Gary R. Lawman ; Joseph D. Linoff, FPGA customizable to accept selected macros.
    상세보기
  11. Chaudhary Kamal, FPGA having logic element carry chains capable of generating wide XOR functions.
    상세보기
  12. Carberry, Richard A.; Young, Steven P.; Bauer, Trevor J., FPGA lookup table with speed read decoder.
    상세보기
  13. Pi, Tao; Crotty, Patrick J., FPGA lookup table with transmission gate structure for reliable low-voltage operation.
    상세보기
  14. Young Steven P. ; Chaudhary Kamal ; Bauer Trevor J., FPGA repeatable interconnect structure with hierarchical interconnect lines.
    상세보기
  15. Kean Thomas A.,GB6 ITX EH88JQ ; Wilkie William A.,GB6 ITX EH106AP, FPGA with parallel and serial user interfaces.
    상세보기
  16. Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray, Field programmable memory array.
    상세보기
  17. Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Seidel Victor Paul ; Zittritsch Terrance John, Field programmable memory array.
    상세보기
  18. Iadanza Joseph Andrew ; Kilmoyer Ralph David ; Laramie Michael Joseph ; Seidel Victor Paul ; Zittritsch Terrance John, Field programmable memory array.
    상세보기
  19. Bennett David Wayne (Louisville CO) Dellinger Eric Ford (Boulder CO) Manaker ; Jr. Walter A. (Boulder CO) Stern Carl M. (Boulder CO) Troxel William R. (Longmont CO) Young Jay Thomas (Louisville CO), Frequency driven layout and method for field programmable gate arrays.
    상세보기
  20. Rees, David Brian, Functionality change by bond optioning decoding.
    상세보기
  21. Southgate Timothy J. ; Wenzler Michael, Graphic editor for block diagram level design of circuits.
    상세보기
  22. Rostoker Michael D. ; Koford James S. ; Scepanovic Ranko ; Jones Edwin R. ; Padmanahben Gobi R. ; Kapoor Ashok K. ; Kudryavtsev Valeriy B.,RUX ; Andreev Alexander E.,RUX ; Aleshin Stanislav V.,RUX ; , Hexagonal field programmable gate array architecture.
    상세보기
  23. Bauer, Trevor J., High-speed lookup table circuits and methods for programmable logic devices.
    상세보기
  24. Laramie Michael J., Interconnect structure between heterogeneous core regions in a programmable array.
    상세보기
  25. Goetting F. Erich (Cupertino CA) Trimberger Stephen M. (San Jose CA), Logic cell for field programmable gate array having optional internal feedback and optional cascade.
    상세보기
  26. New Bernard J. (Los Gatos CA), Logic structure and circuit for fast carry.
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  27. Norman Kevin A. ; Patel Rakesh H. ; Sample Stephen P. ; Butts Michael R., Look-up table based logic element with complete permutability of the inputs to the secondary signals.
    상세보기
  28. Chirania,Manoj; Kondapalli,Venu M., Lookup table circuit optionally configurable as two or more smaller lookup tables with independent inputs.
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  29. Chiang David (Saratoga CA) Lee Napoleon W. (Fremont CA) Ho Thomas Y. (Milpitas CA) Harrison David A. (Cupertino CA) Kucharewski ; Jr. Nicholas (Pleasanton CA) Seltzer Jeffrey H. (San Jose CA), Macrocell with product-term cascade and improved flip flop utilization.
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  30. Clinton Kim P. N. ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Seidel Victor Paul ; Zittritsch Terrance John, Memory cells for field programmable memory array.
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  31. Larsen Wendell Ray (Essex Junction VT) Keyser Frank Ray (Colchester VT) Worth Brian A. (Milton VT), Memory mapping method and apparatus to fold sparsely populated structures into densely populated memory columns or rows.
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  32. Conn ; Jr. Robert O., Method and apparatus for measuring localized voltages on programmable integrated circuits.
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  33. Doyle Stephen J., Method and apparatus for support of multiple memory types in a single memory socket architecture.
    상세보기
  34. Gould Scott W. (So. Burlington VT), Method and system for enhanced drive in programmmable gate arrays.
    상세보기
  35. Fuller Christine Marie ; Hartman Steven Paul ; Millham Eric Ernest, Method and system for optimizing a critical path in a field programmable gate array configuration.
    상세보기
  36. Craft David John ; Gould Scott Whitney ; Keyser ; III Frank Ray ; Worth Brian, Method and system for programming a gate array using a compressed configuration bit stream.
    상세보기
  37. Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable function within a chip to enable configurable I/O signal timing characteristics.
    상세보기
  38. Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable function within a standard cell chip for repair of logic circuits.
    상세보기
  39. Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable interconnect within an ASIC for configuring the ASIC.
    상세보기
  40. Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of an embedded field programmable gate array interconnect for flexible I/O connectivity.
    상세보기
  41. Baxter, Glenn A., Method for controlling timing in reduced programmable logic devices.
    상세보기
  42. Glenn A. Baxter, Method for converting programmable logic devices into standard cell devices.
    상세보기
  43. Schiefele, Walter P.; Krueger, Robert O., Method for creating circuit redundancy in programmable logic devices.
    상세보기
  44. Trimberger, Stephen M., Method for making large-scale ASIC using pre-engineered long distance routing structure.
    상세보기
  45. Baxter, Glenn A., Method for managing database models for reduced programmable logic device components.
    상세보기
  46. Trimberger Stephen M. (San Jose CA), Method for programming an FPLD using a library-based technology mapping algorithm.
    상세보기
  47. Trimberger Stephen M. (San Jose CA), Method for programming an FPLD using a library-based technology mapping algorithm.
    상세보기
  48. Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Zittritsch Terrance John, Method of operating a field programmable memory array with a field programmable gate array.
    상세보기
  49. Kelem Steven H. ; Lawman Gary R., On-chip logic analysis and method for using the same.
    상세보기
  50. Chaudhary Kamal ; Nag Sudip K., Post-placement residual overlap removal method for core-based PLD programming process.
    상세보기
  51. Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Zittritsch Terrance John, Programmable address decoder for field programmable memory array.
    상세보기
  52. Gould Scott Whitney ; Keyser ; III Frank Ray ; Larsen Wendell Ray ; Worth Brian Allen, Programmable array interconnect latch.
    상세보기
  53. Clinton Kim P. N. (Essex Junction VT) Gould Scott W. (South Burlington VT) Hartman Steven P. (Jericho VT) Iadanza Joseph A. (Hinesburg VT) Keyser ; III Frank R. (Colchester VT) Millham Eric E. (St. G, Programmable array interconnect network.
    상세보기
  54. Iadanza Joseph Andrew ; Keyser ; III Frank Ray, Programmable bit line drive modes for memory arrays.
    상세보기
  55. El Gamal Abbas A. (Palo Alto CA) El-Ayat Khaled A. (Cupertino CA) Greene Jonathan W. (Palo Alto CA) Guo Ta-Pen R. (Cupertino CA) Reyneri Justin M. (Los Altos CA), Programmable interconnect architecture.
    상세보기
  56. New Bernard J. ; Carberry Richard A., Programmable logic device having configurable logic blocks with user-accessible input multiplexers.
    상세보기
  57. Baxter, Glenn A., Programmable logic device structures in standard cell devices.
    상세보기
  58. Iadanza Joseph Andrew, Programmable parity checking and comparison circuit.
    상세보기
  59. Iadanza Joseph Andrew, Programmable read ports and write ports for I/O buses in a field programmable memory array.
    상세보기
  60. Darling, Roy D.; Shimanek, Schuyler E.; Davies, Jr., Thomas J., Programming on-the-fly (OTF).
    상세보기
  61. New Bernard J. ; Johnson Robert Anders ; Wittig Ralph ; Mohan Sundararajarao, Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM.
    상세보기
  62. Ochotta Emil S. ; Wieland Douglas P., Routing architecture using a direct connect routing mesh.
    상세보기
  63. Eric R. Keller ; Steven A. Guccione ; Delon Levi, Run-time routing for programmable logic devices.
    상세보기
  64. Clinton Kim P. N. ; Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Kilmoyer Ralph David ; Laramie Michael Joseph ; Seidel Victor Paul ; Zittritsch Terrance John, Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array.
    상세보기
  65. Zhou,Shi dong, Structures and methods of implementing a pass gate multiplexer with pseudo-differential input signals.
    상세보기
  66. Elftmann, Daniel; Speers, Theodore; Kundu, Arunangshu, Synchronous first-in/first-out block memory for a field programmable gate array.
    상세보기
  67. Iadanza Joseph Andrew (Hinesburg VT), System and method for dynamically reconfiguring a programmable gate array.
    상세보기
  68. Gould Scott Whitney (Burlington VT), System for enhanced drive in programmable gate arrays.
    상세보기
  69. Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Kilmoyer Ralph David ; Laramie Michael Joseph, System for implementing write, initialization, and reset in a memory array using a single cell write port.
    상세보기

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  3. Rohe,Andre; Teig,Steven, Concurrent optimization of physical design and operational cycle assignment.
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  4. Schmit, Herman; Huang, Randy Renfu, Configurable IC having a routing fabric with storage elements.
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  5. Teig, Steven, Configurable IC having a routing fabric with storage elements.
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  6. Teig, Steven; Schmit, Herman; Huang, Randy Renfu, Configurable IC having a routing fabric with storage elements.
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  8. Teig, Steven; Redgrave, Jason, Configurable IC with error detection and correction circuitry.
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  9. Teig, Steven; Schmit, Herman; Redgrave, Jason; Chandra, Vikas, Configurable IC with interconnect circuits that also perform storage operations.
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  10. Teig, Steven; Caldwell, Andrew; Redgrave, Jason, Configurable ICs that conditionally transition through configuration data sets.
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  19. Teig, Steven; Ebeling, Christopher D.; Voogel, Martin; Caldwell, Andrew, Configurable storage elements.
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  21. Chandler, Trevis; Redgrave, Jason; Voogel, Martin, Configuration context switcher.
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  23. Chandler, Trevis; Entjer, Joe; Voogel, Martin; Redgrave, Jason, Configuration context switcher with a clocked storage element.
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  30. Redgrave, Jason; Voogel, Martin; Teig, Steven, Controllable storage elements for an IC.
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  31. Ebeling, Christopher D.; Chandler, Trevis, Delaying start of user design execution.
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  32. Hutchings, Brad; Teig, Steven, Dynamically tracking data values in a configurable IC.
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  33. Zhang, Wei; Jha, Niraj K.; Shang, Li, Hybrid nanotube/CMOS dynamically reconfigurable architecture and an integrated design optimization method and system therefor.
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  34. Zhang, Wei; Jha, Niraj K.; Shang, Li, Hybrid nanotube/CMOS dynamically reconfigurable architecture and system therefore.
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  35. Pugh, Daniel J.; Caldwell, Andrew, IC that efficiently replicates a function to save logic and routing resources.
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  36. Hutchings, Brad, IC with deskewing circuits.
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  37. Hutchings, Brad, IC with deskewing circuits.
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  39. Miller, Marc; Teig, Steven; Hutchings, Brad; Thom, Danny, Integrated circuit (IC) with primary and secondary networks and device containing such an IC.
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  40. Redgrave, Jason; Schmit, Herman, Method and apparatus for accessing contents of memory cells.
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  41. Redgrave, Jason, Method and apparatus for accessing stored data in a reconfigurable IC.
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  42. Caldwell, Andrew; Teig, Steven, Method and apparatus for function decomposition.
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  43. Redgrave, Jason; Caldwell, Andrew; Teig, Steven, Method and apparatus for performing an operation with a plurality of sub-operations in a configurable IC.
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  44. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Method of mapping a user design defined for a user design cycle to an IC with multiple sub-cycle reconfigurable circuits.
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  45. Fox, Brian, Micro-granular delay testing of configurable ICs.
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  46. Olgiati, Andrea; Baker, Matthew Pond; Teig, Steven, Non-intrusive monitoring and control of integrated circuits.
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  66. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.
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  67. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.
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  68. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.
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  70. Huang, Randy R.; Voogel, Martin; Hu, Jingcao; Teig, Steven, System and method for reducing reconfiguration power.
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  71. Huang, Randy R.; Voogel, Martin; Hu, Jingcao; Teig, Steven, System and method for reducing reconfiguration power usage.
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  72. Huang, Randy R.; Voogel, Martin; Hu, Jingcao; Teig, Steven, System and method for reducing reconfiguration power usage.
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  76. Hutchings, Brad; Caldwell, Andrew; Teig, Steven, Translating a user design in a configurable IC for debugging the user design.
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  82. Hutchings, Brad; Redgrave, Jason; Huang, Dai; Teig, Steven, Trigger circuits and event counters for an IC.
    상세보기
  83. Redgrave, Jason, User registers implemented with routing circuits in a configurable IC.
    상세보기
  84. Redgrave, Jason, User registers implemented with routing circuits in a configurable IC.
    상세보기
  85. Redgrave, Jason, Users registers implemented with routing circuits in a configurable IC.
    상세보기
  86. Schmit, Herman; Teig, Steven, VPA interconnect circuit.
    상세보기
  87. Schmit,Herman; Teig,Steven, VPA logic circuits.
    상세보기

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