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Method and apparatus for secure configuration of a field programmable gate array 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-011/30
출원번호 US-0747759 (2000-12-21)
우선권정보 GB-9930145.9(1999-12-22)
발명자 / 주소
  • Kean,Thomas A.
출원인 / 주소
  • Algotronix, Ltd.
대리인 / 주소
    Orrick, Herrington & Sutcliffe LLP
인용정보 피인용 횟수 : 70  인용 특허 : 54

초록

초록이 없습니다.

대표청구항

대표청구항이 없습니다.

이 특허에 인용된 특허 (54)

  1. Redman Scott ; Mak Dennis ; Terrill Richard, Access restriction to circuit designs.
  2. Janssen John Jerome ; Olsen Steven J., Apparatus and method for securing electronic information in a wireless communication device.
  3. Bright Michael W. ; Fuchs Kenneth Carl ; Marquardt Kelly Jo, Apparatus and method of reading a program into a processor.
  4. Roselli, Leonard, Arrangement for reading an absolute position encoder for determining the operating position of a break handle.
  5. Sehr Richard P., Card system and methods utilizing collector cards.
  6. Hoffman Jeffrey D., Cipher core in a content protection system.
  7. Johnstone ; Richard, Computer software security system.
  8. Kean Thomas A.,GBX, Configurable cellular array.
  9. Trimberger Stephen M., Configurable electronic device which is compatible with a configuration bitstream of a prior generation configurable ele.
  10. Rangasayee Krishna, Configuration eprom with programmable logic.
  11. Erickson Charles R., Configuration stream encryption.
  12. Lawman Gary R., Configuring an FPGA using embedded memory.
  13. Best Robert M. (16016 9th Ave. NE. Seattle WA 98155), Crypto microprocessor that executes enciphered programs.
  14. Plants, William C., Cyclic redundancy checking of a field programmable gate array having a SRAM memory architecture.
  15. Lai Yi-Sern,TWX ; Chuang I-Yao,TWX ; Chiou Bor-Wen,TWX ; Yang Chin-Ning,TWX, DES cipher processor for full duplex interleaving encryption/decryption service.
  16. Austin Kenneth (Northwich GBX), Data security arrangements for semiconductor programmable devices.
  17. Klein, Dean A., Data security for digital data storage.
  18. Lawman Gary R., Decoder structure and method for FPGA configuration.
  19. Hampson Bradford E. (Framingham MA), Digital computer system for executing encrypted programs.
  20. Kocher, Paul C.; Jaffe, Joshua M.; Jun, Benjamin C., Digital content protection method and apparatus.
  21. Cohen Joshua L. ; Dean Cecil A. ; du Breuil Thomas L. ; Heer Daniel Nelson ; Maher David P. ; Poteat Vance Eugene ; Rance Robert John, Electronic identifiers for network terminal devices.
  22. Chojnacki, Robert, Encryption method for distribution of data.
  23. Erickson Charles R. ; Tavana Danesh ; Holen Victor A., Encryption of configuration stream.
  24. Burnham James L. ; Lawman Gary R. ; Linoff Joseph D., FPGA customizable to accept selected macros.
  25. Paul Jeffrey Garnett GB, Field programmable gate arrays.
  26. Yearsley Gyle (Boise ID) Richards Grant (Meridian ID), Firmware encryption for microprocessor/microcomputer.
  27. Karp Alan H. (Palo Alto CA), Hardware assist for protecting PC software.
  28. Erickson Brian D., Integrated circuit packaged for receiving another integrated circuit.
  29. Pastor Jose (Westport CT) Barton Maya R. (Ridgefield CT), Method and apparatus for generating encryption/decryption key.
  30. Sung Chiakang ; Wang Bonnie I., Method and apparatus for securing programming data of a programmable logic device.
  31. Sung Chiakang ; Wang Bonnie I., Method and apparatus for securing programming data of programmable logic device.
  32. Lawman Gary R., Method for generating a secure macro element of a design for a programmable IC.
  33. Wong Albert C. K. (Golden Valley MN) Jurewicz Romuald M. (St. Louis Park MN) McCormack Michael D. (Robbinsdale MN), Method of determining the condition of a back-up battery for a real time clock.
  34. Choi Byeng-Sun,KRX, Multi-bit memory device having error check and correction circuit and method for checking and correcting data errors therein.
  35. Rao Kameswara K. ; Voogel Martin L., Non-volatile storage for standard CMOS integrated circuits.
  36. Chiu Ming-Yee (Mt. Laurel NJ), On-chip microprocessor instruction decoder having hardware for selectively bypassing on-chip circuitry used to decipher.
  37. Curd Derek R. ; Jacobson Neil G. ; Diba Sholeh ; Lee Napoleon W. ; Ku Wei-Yi ; Rao Kameswara K., Overridable data protection mechanism for PLDs.
  38. Lawman Gary R., PROM with built-in JTAG capability for configuring FPGAs.
  39. Thiriet Fabien P. (Orleans FRX), Process for protecting components of smart or chip cards from fraudulent use.
  40. Hazard, Michel, Process for storage and use of sensitive information in a security module and the associated security module.
  41. Chiang David (Saratoga CA) Ho Thomas Y. (Milpitas CA) Ku Wei-Yi (Cupertino CA) Simmons George H. (Sunnyvale CA) Barker Robert W. (San Jose CA), Programmable logic device having security elements located amongst configuration bit location to prevent unauthorized re.
  42. Walter Paul Alan ; McGrogan ; Jr. Ellwood Patrick ; Kleidermacher Mike, Programmable telecommunications security module for key encryption adaptable for tokenless use.
  43. Stefik, Mark J.; Pirolli, Peter L. T., Repository with security class and method for use thereof.
  44. Matyas, Jr., Stephen Michael; Peyravian, Mohammad; Roginsky, Allen Leonid; Zunic, Nevenko, Secure data storage and retrieval with key management and user authentication.
  45. Candelore Brant ; Sprunk Eric, Secure processor with external memory using block chaining and block re-ordering.
  46. Apland James M. ; Eaton David D. ; Chan Andrew K., Security antifuse that prevents readout of some but not other information from a programmed field programmable gate arr.
  47. Nemoto Masahisa (Tokyo JPX), Semiconductor integrated circuit device having main power terminal and backup power terminal independently of each other.
  48. Gaffney, Jr., John E., Software cryptographic apparatus and method.
  49. Curran Kevin G. (Sudbury MA) Golson Steven E. (Wayland MA) Rode Christian S. (Cambridge MA), Software protection methods and apparatus.
  50. Buer Mark Leonard, Standard cell ring oscillator of a non-deterministic randomizer circuit.
  51. Kelem Steven H. ; Burnham James L., System and method for PLD bitstream encryption.
  52. Hair, Arthur R., System and method for manipulating a computer file and/or program.
  53. Hartman ; Jr. Robert C. (Woodside CA), System for seamless processing of encrypted and non-encrypted data and instructions.
  54. Guttag Karl M. (Houston TX), Use of implant process for programming ROM type processor for encryption.

이 특허를 인용한 특허 (70)

  1. Redgrave, Jason; Hutchings, Brad; Teig, Steven; Schmit, Herman; Khubchandani, Teju, Accessing multiple user states concurrently in a configurable IC.
  2. Xia, Renxin; Joyce, Juju; Prasad, Nitin; Veenstra, Kerry; Duwel, Keith, Apparatus and methods for communicating with programmable devices.
  3. Miller, Greg, Automatic configuration of devices upon introduction into a networked environment.
  4. Miller, Greg, Automatic configuration of devices upon introduction into a networked environment.
  5. Atta, Islam; Pettey, Christopher Joseph; Khan, Asif; Johnson, Robert Michael; Davis, Mark Bradley; Izenberg, Erez; Bshara, Nafea; Constantinides, Kypros, Configurable logic platform.
  6. Redgrave, Jason; Khubchandani, Teju; Schmit, Herman, Configuration network for an IC.
  7. Oh, Jong-Min; Song, Ho-Yong; Jang, Seong-Jin, Data loading circuit and semiconductor memory device comprising same.
  8. Oh, Jong-Min; Song, Ho-Young; Jang, Seong-Jin, Data loading circuit and semiconductor memory device comprising same.
  9. Komarla, Eshwari P.; Zimmer, Vincent J.; Bulusu, Mallik, Data security.
  10. Hyde, Roderick A.; Pasch, Nicholas F.; Tegreene, Clarence T., Data security and access tracking in memory.
  11. Trimberger, Stephen M., Deterring reverse engineering.
  12. Hutchings, Brad; Teig, Steven, Dynamically tracking data values in a configurable IC.
  13. Cohen, Ariel; Anand, Abhinav; Aulagnier, Pierre; Cheung, Gerald; Cochinwala, Naveed; Lockwood, Greg; Sundaresan, Ganesh; Tadikonda, Susheel; Venkataraghavan, Vikram; Wong, Ming, Efficient data transfer between servers and remote peripherals.
  14. Martin, Grégorie; Cavalli, David; Firmin, Fabian, Embedded FPGA with multiple configurable flexible logic blocks instantiated and interconnected by abutment.
  15. Celikkan, Ufuk; Conklin, William C.; Mullen, Shawn P.; Shankar, Ravi A., Encrypted file system mechanisms.
  16. Celikkan,Ufuk; Conklin,William C.; Mullen,Shawn P.; Shankar,Ravi A., Encryption apparatus and method for providing an encrypted file system.
  17. Schultz,David P., Error correction for multiple word read.
  18. Hyde, Roderick A.; Pasch, Nicholas F.; Tegreene, Clarence T., Error correction with non-volatile memory on an integrated circuit.
  19. Wallmark,Magnus; Jonsson,Mattias, Exchangeable module for additional functionality.
  20. Tahiri, Farid; Garaccio, Pierre Dominique Xavier, Flexible logic unit.
  21. Hyde, Roderick A.; Pasch, Nicholas F.; Tegreene, Clarence T., Flexible processors and flexible memory.
  22. Venkataraghavan, Vikram; Wong, Ming; Jain, Vipul; Tang, Cheng; Shah, Shreyas; Davar, Jonathan; Dvorkin, Mike, High availability and I/O aggregation for server environments.
  23. Hutchings, Brad, IC with deskewing circuits.
  24. Nakanishi, Hironori; Furuhashi, Kana, Information storage apparatus, information storage method, and electronic device.
  25. Miller, Marc; Teig, Steven; Hutchings, Brad, Integrated circuit (IC) with primary and secondary networks and device containing such an IC.
  26. Miller, Marc; Teig, Steven; Hutchings, Brad; Thom, Danny, Integrated circuit (IC) with primary and secondary networks and device containing such an IC.
  27. Hutchings, Brad; Redgrave, Jason, Integrated circuit with delay selecting input selection circuitry.
  28. Hyde, Roderick A.; Pasch, Nicholas F.; Tegreene, Clarence T., Intelligent monitoring for computation in memory.
  29. Hyde, Roderick A.; Pasch, Nicholas F.; Tegreene, Clarence T., Memory circuitry including computational circuitry for performing supplemental functions.
  30. Langhammer, Martin, Method and apparatus for protecting designs in SRAM-based programmable logic devices and the like.
  31. Cizas, Jurijus; Eswarahally, Shrinath; Laackmann, Peter; Gammel, Berndt; Stafford, Mark; Borchert, Joerg, Method and system for controlling a device.
  32. Cizas, Jurijus; Eswarahally, Shrinath; Laackmann, Peter; Gammel, Berndt; Stafford, Mark; Borchet, Joerg, Method and system for controlling a device.
  33. Cizas, Jurijus; Eswarahally, Shrinath; Laackmann, Peter; Gammel, Berndt; Stafford, Mark; Borchert, Joerg, Method and system for transferring information to a device.
  34. Cizas, Jurijus; Eswarahally, Shrinath; Laackmann, Peter; Gammel, Berndt; Stafford, Mark; Borchert, Joerg, Method and system for transferring information to a device.
  35. Langton, Philip Sydney, Methods, apparatuses, and products for a secure circuit.
  36. Cohen, Ariel; Krishnamurthi, Ashok, Network virtualization over infiniband.
  37. McLean, Ian; Keating, Stephen Mark, Programmable logic device.
  38. Hyde, Roderick A.; Pasch, Nicholas F.; Tegreene, Clarence T., Random number generator functions in memory.
  39. Aulagnier,Pierre, Randomized self-checking test system.
  40. Hyde, Roderick A.; Pasch, Nicholas F.; Tegreene, Clarence T., Redundancy for loss-tolerant data in non-volatile memory.
  41. Cohen, Ariel; Krishnamurthi, Ashok; Krishnamurthy, Viswanath; Salzmann, Frank; Allison, David S.; Tang, Cheng, Remote shared server peripherals over an Ethernet network for resource virtualization.
  42. Sundaresan, Ganesh; Lim, Raymond; Shah, Shreyas, Resource virtualization mechanism including virtual host bus adapters.
  43. Tahiri, Farid; Garaccio, Pierre Dominique Xavier, Robust flexible logic unit.
  44. Tahiri, Farid; Garaccio, Pierre Dominique Xavier, Robust flexible logic unit.
  45. Hutchings, Brad; Redgrave, Jason; Khubchandani, Teju; Schmit, Herman; Teig, Steven, Runtime loading of configuration data in a configurable IC.
  46. Hutchings, Brad; Redgrave, Jason; Khubehandani, Teju; Schmit, Herman; Teig, Steven, Runtime loading of configuration data in a configurable IC.
  47. Hofstee, H Peter; Kahle, James A.; Paolini, Michael A., Secure dynamically reconfigurable logic.
  48. Woodall, Thomas R., Secure field-programmable gate array (FPGA) architecture.
  49. Woodall, Thomas R., Secure field-programmable gate array (FPGA) architecture.
  50. Borchert, Joerg; Cizas, Jurijus; Eswarahally, Shrinath; Stafford, Mark; Krishnamurthy, Rajagopalan, Secure manufacturing of programmable devices.
  51. Borchert, Joerg; Cizas, Jurijus; Eswarahally, Shrinath; Stafford, Mark; Krishnamurthy, Rajagopalan, Secure operation of programmable devices.
  52. Kaabouch, Majid; Croguennec, Alexandre; Le Cocquen, Eric, Secure software download.
  53. Devadas, Srinivas; Ziola, Thomas J., Securely field configurable device.
  54. Lewis, James M.; Haddock, Joey R.; Walther, Dane R., Self-modifying FPGA for anti-tamper applications.
  55. Lewis, James M.; Haddock, Joey R.; Walther, Dane R., Self-modifying FPGA for anti-tamper applications.
  56. Bose, Pradip; Kursun, Eren; Rivers, Jude A.; Zyuban, Victor, Semiconductor chip repair by stacking of a base semiconductor chip and a repair semiconductor chip.
  57. Bose, Pradip; Kursun, Eren; Rivers, Jude A.; Zyuban, Victor, Semiconductor chip repair by stacking of a base semiconductor chip and a repair semiconductor chip.
  58. Mori, Yasufumi; Azuma, Katsuhiko; Miura, Manabu, Semiconductor device, unique ID of semiconductor device and method for verifying unique ID.
  59. Watanabe,Atsushi; Rinoie,Noburu; Kobayashi,Takamitsu, Semiconductor integrated circuit with function to manage license information.
  60. Sauber, William F.; Huber, Gary D., System and method for configuring information handling system integrated circuits.
  61. Fayad, Camil; Li, John K.; Sutter, Siegfried, System and method for providing dynamically authorized access to functionality present on an integrated circuit chip.
  62. Teig, Steven, System in package and method of creating system in package.
  63. La Fever, George Bernard; Flaum, Iser B., Systems and methods of device authentication including features of circuit testing and verification in connection with known board information.
  64. La Fever, George Bernard; Flaum, Iser B., Systems and methods of implementing content validation of microcomputer based circuits.
  65. La Fever, George B.; Yellin, Carmy; Flaum, Iser B.; Muse, David R., Systems and methods of implementing remote boundary scan features.
  66. La Fever, George B.; Yellin, Carmy; Flaum, Iser B.; Muse, David R., Systems and methods of implementing remote boundary scan features.
  67. Hutchings, Brad; Caldwell, Andrew; Teig, Steven, Translating a user design in a configurable IC for debugging the user design.
  68. Hutchings, Brad L.; Redgrave, Jason; Huang, Dai; Teig, Steven, Trigger circuits and event counters for an IC.
  69. Michael,Lachlan; Mihaljevic,Miodrag, Wireless data communication method and apparatus for software download system.
  70. Krishnamurthi, Ashok; Cohen, Ariel, Wireless host I/O using virtualized I/O controllers.
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