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Fault tolerant data communication network 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
  • G06F-013/42
출원번호 US-0454057 (1999-12-02)
발명자 / 주소
  • Doerenberg,Frank M. G.
  • Topic,Michael
출원인 / 주소
  • Honeywell International Inc.
대리인 / 주소
    Black Lowe & Graham PLLC
인용정보 피인용 횟수 : 14  인용 특허 : 60

초록

초록이 없습니다.

대표청구항

대표청구항이 없습니다.

이 특허에 인용된 특허 (60)

  1. Birkedahl Byron F. ; Endrud Douglas G., Aircraft display and control system with virtual backplane architecture.
  2. Marik Mark Douglas ; Palo Robert Anthony ; Waefler Susan E., Apparatus and method for data communication between nodes.
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  7. Santeler Paul (Cypress TX) Thome Gary W. (Houston TX), Burst data transfer to single cycle data transfer conversion and strobe signal conversion.
  8. Sides Chi Kim (Spring TX), Bus deadlock prevention circuit for use with second level cache controller.
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  10. Petersen Hans (Frth-Burgfarrnbach DEX) Stegmann Kurt (Nuremberg DEX), Bus system with address and status conductors.
  11. Sites Richard L. (Boylston MA) Witek Richard T. (Littleton MA), Byte-compare operation for high-performance processor.
  12. Leibe Gerhard (Munich DEX) Weiss Albert (Munich DEX), Circuit arrangement for designational reading of information of a bit group oriented, continuous information stream at a.
  13. Baker Robert Grover (Delray Beach FL) Huynh Duy Quoc (Boca Raton FL) Moeller Dennis Lee (Boca Raton FL) Swingle Paul Richard (Delray Beach FL) Tran Loc Tien (Boca Raton FL) Yong Suksoon (Boca Raton F, Computer system having a DSP local bus.
  14. Turner Jonathan S. (University City MO), Cross-connect for switch modules.
  15. Hutch Frederick S. (Warminster PA), Data communication system.
  16. Sites Richard L. (Boylston MA) Witek Richard T. (Littleton MA), Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system.
  17. Galis Alexandru (London GBX) Richardson Malcolm (Herts GBX) Page Stuart (Herts GBX) Devani Shailen (Middlesex GBX), Expert and data base system and method for communications network.
  18. Frank M. G. Doerenberg ; Michael Topic, Fault tolerant data communication network.
  19. Baker Ernest D. (Boca Raton FL) Dinwiddie ; Jr. John M. (West Palm Beach FL) Grice Lonnie E. (Boca Raton FL) Joyce James M. (Boca Raton FL) Loffredo John M. (Deerfield Beach FL) Sanderson Kenneth R. , Fault tolerant data processing system.
  20. Hashemi Seyed H. (Mission Viejo CA), Fault tolerant digital computer system having two processors which periodically alternate as master and slave.
  21. Morrison Brian D. ; Wienke Creig E. ; Batten Martin R. ; Robillard Michael N., Fault tolerant distributed control system.
  22. Bruckert William F. (Northboro MA) Bissett Thomas D. (Derry NH) Mazur Dennis (Worcester MA) Munzer John (Brookline MA), Fault tolerant, synchronized twin computer system with error checking of I/O communication.
  23. Cutts ; Jr. Richard W. (Georgetown TX) Banton Randall G. (Austin TX) Jewett Douglas E. (Austin TX), Fault-tolerant computer system having switchable I/O bus interface modules.
  24. Cutts ; Jr. Richard W. (Georgetown TX) Banton Randall G. (Austin TX) Jewett Douglas E. (Austin TX), Fault-tolerant computer system with redesignation of peripheral processor.
  25. Cutts ; Jr. Richard W. (Georgetown) Norwood Peter C. (Austin) DeBacker Kenneth C. (Austin) Mehta Nikhil A. (Austin) Jewett Douglas E. (Austin) Allison John D. (Austin TX) Horst Robert W. (Champaign I, Fault-tolerant computer with three independently clocked processors asynchronously executing identical code that are syn.
  26. Hartmann Alfred C., Flexible buffering scheme for inter-module on-chip communications.
  27. Hopkins Martin E. (Chappaqua NY) Warren ; Jr. Henry S. (Ossining NY), Generating efficient code for a computer with dissimilar register spaces.
  28. Anderson, Terry M.; George, William R., High performance switching.
  29. Turner Jonathan S. (University City MO), High speed data link.
  30. Sites Richard L. (Boylston MA) Witek Richard T. (Littleton MA), In-register data manipulation for unaligned byte write using data shift in reduced instruction set processor.
  31. Sites Richard L. (Boylston MA) Witek Richard T. (Littleton MA), In-register data manipulation using data shift in reduced instruction set processor.
  32. Dechant ; Thomas Edward ; Glaser ; Edward Lewis ; Pitt ; Paul Eldred ; Way ; III ; Frederick, Information storage and retrieval system.
  33. Daly Francis W. ; Kuntman Daryal ; Doerenberg Frank ; McElroy James J., Integrated hazard avoidance system.
  34. Daly Francis W. ; Kuntman Daryal ; Doerenberg Frank ; McElroy James J., Integrated hazard avoidance system.
  35. Bennett ; Thomas H. ; Carlow ; Earl F. ; Hepworth ; Edward C. ; Mathys ; Wilbur L. ; Mensch ; Jr. ; William D. ; Orgill ; Rodney H. ; Peddle ; C harles I. ; Wiles ; Michael F., Interrupt system for microprocessor system.
  36. Birkedahl Byron F. ; Eddy Brett A., Low cost redundant communications system.
  37. Bennett Thomas H. (Scottsdale AZ) Carlow Earl F. (Scottsdale AZ) Hepworth Edward C. (Apache Junction AZ) Mathys Wilbur L. (Norristown PA) Mensch ; Jr. William D. (Norristown PA) Orgill Rodney H. (Nor, Master slave registers for interface adaptor.
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  39. Hendel Ariel (Ronkonkoma NY) Brinkerhoff Kenneth W. (Hauppauge NY), Method and apparatus for buffering data within stations of a communication network.
  40. Kreulen Jeffrey Thomas ; Mandyam Sriram Srinivasan ; O'Krafka Brian Walter ; Salamian Shahram ; Raghavan Ramanathan, Method and apparatus for creating a multiprocessor verification environment.
  41. Sites Richard L. (Boylston MA) Witek Richard T. (Littleton MA), Method and apparatus for eliminating branches using conditional move instructions.
  42. Dieffenderfer James N. ; Linzer Harry I. ; Sartorius Thomas Andrew, Method and apparatus for processing null terminated character strings.
  43. Daniels R. Gary (Round Rock TX) Musa Fuad H. (Austin TX) Wilder ; Jr. William B. (Austin TX) Wiles Michael F. (Round Rock TX) Bennett Thomas H. (Scottsdale AZ), Microprocessor having plural internal data buses.
  44. Deal ; Jr. Joseph H. (Clarksburg MD), Microprogrammable TDMA terminal controller.
  45. Buus Henning (Woodinville WA), Multiaxis redundant fly-by-wire primary flight control system.
  46. Bennett Thomas H. (Scottsdale AZ) Carlow Earl F. (Scottsdale AZ) Peddle Charles (Norristown PA) Wiles Michael F. (Phoenix AZ), Multiple interrupt microprocessor system.
  47. Horst Robert W. (Champaign IL), Multiple-processor computer system with asynchronous execution of identical code streams.
  48. Jewett Douglas E. (Austin TX), Multiprocessor system with each processor executing the same instruction sequence and hierarchical memory providing on d.
  49. Lee Tony T. (Bridgewater NJ), Non-blocking copy network for multicast packet switching.
  50. Jackson Michael T. (Houston TX) Fry Walter G. (Spring TX), Processor board having a second level writeback cache system and a third level writethrough cache system which stores ex.
  51. Bruder John E. (Arlington MA), Quantizer control method and apparatus.
  52. Garg Sanjiv (Fremont CA) Lentz Derek J. (Los Gatos CA) Nguyen Le T. (Monte Sereno CA) Chen Sho L. (Saratoga CA), RISC microprocessor architecture implementing multiple typed register sets.
  53. Garg Sanjiv (Fremont CA) Lentz Derek J. (Los Gatos CA) Nguyen Le T. (Monte Sereno CA) Chen Sho L. (Saratoga CA), RISC microprocessor architecture implementing multiple typed register sets.
  54. Garg Sanjiv (Fremont CA) Lentz Derek J. (Los Gatos CA) Nguyen Le Trong (Monte Sereno CA) Chen Sho Long (Saratoga CA), RISC microprocessor architecture implementing multiple typed register sets.
  55. Moorwood Charles A. (Sunnyvale CA) Singh Charan J. (Fairfield CA) Holland Dennis E. (Morgan Hill CA) Cimino Daniel J. (Mountan View CA) Vo Howard Q. (San Jose CA) Yeung Vickie M. (San Francisco CA) C, Segment tester for a repeater interface controller.
  56. Sonnier David P. (Austin TX) Bunton Wiliam P. (Austin TX) Cutts ; Jr. Richard W. (Georgetown TX) Klecka James S. (Lexington TX) Krause John C. (Georgetown TX) Watson William J. (Austin TX) Zalzala Li, Synchronized data transmission between elements of a processing system.
  57. Divine James S. (Austin TX) Studor Charles F. (Austin TX), System and method for executing branch on bit set/clear instructions using microprogramming flow.
  58. Duncan Kathleen Anne (Santa Cruz CA), System including ATA sequencer microprocessor which executes sequencer instructions to handle plurality of real-time eve.
  59. Bennett ; Thomas H. ; Carlow ; Earl F. ; Hepworth ; Edward C. ; Mathys ; Wilbur L. ; Mensch ; Jr. ; William D. ; Orgill ; Rodney H. ; Peddle ; C harles I. ; Wiles ; Michael F., Valid memory address enable system for a microprocessor system.
  60. Morrison Brian D. ; Batten Martin R. ; Robillard Michael N. ; Wienke Creig E., Voting node for a distributed control system.

이 특허를 인용한 특허 (14)

  1. Stoner, Paul Douglas, Apparatus and method pertaining to light-based power distribution in a vehicle.
  2. Stoner, Paul Douglas; Vlad, Ovidiu Gabriel, Apparatus and method pertaining to light-based power distribution in a vehicle.
  3. Stoner, Paul Douglas; Vlad, Ovidiu Gabriel, Apparatus and method pertaining to provision of a substantially unique aircraft identifier via a source of power.
  4. Davies, Robin William, High-integrity data transmission system.
  5. Mazuk, Daniel E.; Miller, David A.; Klein, Clifford R.; Chau, Savio N.; Anderson, Eric N., Integrated modular avionics system with distributed processing.
  6. Lee, Donald B; Mitchell, Bradley J; Schultz, Larry R, Mechanically isolated wireless communications system and method.
  7. Stoner, Paul Douglas, Method and apparatus for handling data and aircraft employing same.
  8. Stoner, Paul Douglas; Vlad, Ovidiu Gabriel, Method and apparatus for handling data and aircraft employing same.
  9. Darby, Michael; Duke, Brant, Multiple aircraft engine control system and method of communicating data therein.
  10. Jackson, Timothy E., Processing packets in an aircraft network data processing system.
  11. Caule, Nicolas; Marques, Andre; Raynaud, Garance, Reconfiguration process of an aircraft environment surveillance device.
  12. Griffith, Scot E., Systems and methods for arbitrating sensor and actuator signals in a multi-channel control system.
  13. Dam, Hai Thanh; McLaughlin, Daniel Lee; Verlenich, Nick, Techniques for facilitating communication between networked nodes.
  14. Ungermann, Jörn; Fuhrmann, Peter, Time-triggered communication system and method for the synchronization of a dual-channel network.
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