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Chip debugging using incremental recompilation and register insertion 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-011/00
출원번호 US-0774731 (2004-02-09)
발명자 / 주소
  • Marti,Philippe
  • Jervis,Mark
  • Nixon,Gregor
출원인 / 주소
  • Altera Corporation
대리인 / 주소
    Beyer Weaver LLP
인용정보 피인용 횟수 : 78  인용 특허 : 66

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이 특허에 인용된 특허 (66)

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  2. Jamal Kamran (Sunnyvale CA), Built-in self test for integrated circuits having read/write memory.
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  3. Nixon,Gregor; Jervis,Mark; Pan,Zhengjun; Silva,Gihan De; Perry,Steven, Chip debugging using incremental recompilation.
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  4. Couts-Martin Chris ; Herrmann Alan, Configuration memory integrated circuit.
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  5. Easterday John L. (Portland OR), Data acquisition system for capturing and storing clustered test data occurring before and after an event of interest.
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  6. Norman Kevin A. ; Patel Rakesh H. ; Sample Stephen P. ; Butts Michael R., Diagnostic interface system for programmable logic system development.
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  7. Heile Francis B., Electronic design automation tool for display of design profile.
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  8. Alan L. Herrmann ; Greg P. Nugent, Embedded logic analyzer for a programmable logic device.
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  10. Sample Stephen P. ; Bershteyn Mikhail ; Butts Michael R. ; Bauer Jerry R., Emulation system with time-multiplexed interconnect.
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  11. Beenstra Kerry ; Rangasayee Krishna ; Herrmann Alan L., Enhanced embedded logic analyzer.
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  12. Kerry Veenstra ; Krishna Rangasayee ; Alan L. Herrmann, Enhanced embedded logic analyzer.
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  13. Veenstra Kerry ; Rangasayee Krishna ; Herrmann Alan L., Enhanced embedded logic analyzer.
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  14. Veenstra, Kerry; Rangasayee, Krishna; Herrmann, Alan L., Enhanced embedded logic analyzer.
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  15. Hoyer, Bryan H.; Fairman, Michael C., Gaining access to internal nodes in a PLD.
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  16. Bruce Pedersen ; Francis B. Heile ; Marwan Adel Khalaf ; David Wolk Mendel, Generation of sub-netlists for use in incremental compilation.
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  17. Brebner, Gordon J., Gigabit router on a single programmable logic device.
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  18. Beausang James ; Ellingham Chris ; Robinson Markus F. ; Walker Robert, Hierarchical scan architecture for design for test applications.
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  19. Beausang James ; Ellingham Chris ; Robinson Markus F. ; Walker Robert, Hierarchical scan architecture for design for test applications.
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  20. Butts Michael R. (Portland OR) Batcheller Jon A. (Newberg OR), Hierarchically connected reconfigurable logic assembly.
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  21. Guccione Steven A., Interactive dubug tool for programmable circuits.
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  22. Heile Francis B. ; Rawls Tamlyn V., Interface for compiling project variations in electronic design environments.
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  23. Stewart Kem ; Selvidge Charles W. ; Crouch Kenneth ; Wong Marina ; Seneski Mark, Logic analysis system for logic emulation systems.
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  24. Nakajima Takayuki (Gyoda JPX) Aoki Tetsuo (Kohnosu JPX) Kobayashi Katsumi (Gyoda JPX) Akiyama Noboru (Kumagaya JPX), Logic analyzer.
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  27. Haag George A. ; Byrne Patrick J., Method and apparatus for accessing internal integrated circuit signals.
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  28. Theron, Conrad A.; St. Pierre, Jr., Donald H., Method and apparatus for changing execution code for a microcontroller on an FPGA interface device.
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  29. Liu Dick L. (Saratoga CA) Li Jeong-Tyng (Cupertino CA) Huang Thomas B. (San Jose CA) Choi Kenneth S. K. (San Jose CA), Method and apparatus for debugging reconfigurable emulation systems.
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  30. Chen Benjamin ; Macliesh Peter ; Wang Albert, Method and apparatus for entry of timing constraints.
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  31. Jamal Kamran (Sunnyvale CA), Method and apparatus for making integrated circuits with built-in self-test.
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  32. Patel Rakesh H. ; Costello John ; Wong Myron, Method and apparatus for monitoring or forcing an internal node in a programmable device.
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  33. Brebner, Gordon J., Method and apparatus for multithreading.
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  34. Fleisher Evgeny G., Method and apparatus for testing a logic design of a programmable logic device.
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  35. Fang, Ying, Method and apparatus for testing an embedded device.
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  36. Nee, Patrick; Fenton, William; Harvey, Ciaran; Simmonds, Malcolm, Method and system for testing microprocessor based boards in a manufacturing environment.
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  37. Butts Michael R. ; Batcheller Jon A., Method for performing simulation using a hardware emulation system.
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  38. Suryanarayana Duggirala ; Rohit Kapur ; Thomas W. Williams, Method for placement-based scan-in and scan-out ports selection.
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  39. Jesse H. Jenkins, IV ; Walter H. Edmondson, Method for remotely testing microelectronic device over the internet.
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  40. Butts, Michael R.; Batcheller, Jon A., Method of using electronically reconfigurable logic circuits.
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  41. Uhling Thomas F. (Monument CO) Dascher David J. (Colorado Springs CO) Rush Kenneth (Colorado Springs CO) Griggs Keith C. (Colorado Springs CO), Multiplexing electronic test probe.
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  42. Jacobson,Neil G., Network based diagnostic system and method for software reconfigurable systems.
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  43. Whitsel Ronald J. (Beaverton OR) Hobbs William A. (Beaverton OR), On-chip in-circuit-emulator memory mapping and breakpoint register modules.
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  44. Kelem Steven H. ; Lawman Gary R., On-chip logic analysis and method for using the same.
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  45. Manela Philip R. ; Birch Peter R. ; Lin John C. ; Ullum Daniel R., Output pin for selectively outputting one of a plurality of signals internal to a semiconductor chip according to a prog.
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  46. Patel Rakesh H. ; Norman Kevin A., Partially reconfigurable programmable logic device.
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  47. Khoche Ajay ; Singh Harbinder ; Goswami Dhiraj ; Martin Denis, Pre-synthesis test point insertion.
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  51. El Gamal Abbas A. (Palo Alto CA) El-Ayat Khaled A. (Cupertino CA) Greene Jonathan W. (Palo Alto CA) Guo Ta-Pen R. (Cupertino CA) Reyneri Justin M. (Los Altos CA), Programmable interconnect architecture.
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  52. Kaplinsky Cecil H. (Palo Alto CA), Programmable logic device.
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  53. Ketan Zaveri ; Christopher F. Lane ; Srinivas T. Reddy ; Andy L. Lee ; Cameron R. McClintock ; Bruce B. Pedersen, Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits.
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  57. Sample Stephen P. (Mountain View CA) D\Amour Michael R. (Los Altos Hills CA) Payne Thomas S. (Union City CA), Reconfigurable hardware emulation system.
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  58. Patel Rakesh H. ; Norman Kevin A., Sample and load scheme for observability of internal nodes in a PLD.
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  59. Patel Rakesh H. ; Norman Kevin A., Sample and load scheme for observability of internal nodes in a PLD.
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  60. Butts Michael R. (Portland OR) Batcheller Jon A. (Newberg OR), Structures and methods for adding stimulus and response functions to a circuit design undergoing emulation.
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  61. Duggirala, Suryanarayana; Kapur, Rohit; Williams, Thomas W., System and method for high-level test planning for layout.
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  63. Alfke Peter H., System for preventing radiation failures in programmable logic devices.
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  64. Dastidar,Jayabrata Ghosh; Wright,Adam; Pang,Hung Hing Anthony; Vo,Binh; Nagarandal,Ajay; Tracy,Paul J.; Harms,Michael, Techniques for automatically generating tests for programmable circuits.
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  65. El-Ayat Khaled A. (Cupertino CA) Chang Jia-Hwang (Cupertino CA), Testability architecture and techniques for programmable interconnect architecture.
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