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High speed promotion mechanism suitable for lock acquisition in a multiprocessor data processing system 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/46
  • G06F-012/14
  • G06F-015/00
출원번호 US-0268729 (2002-10-10)
발명자 / 주소
  • Arimilli,Ravi Kumar
  • Williams,Derek Edward
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Dillon & Yudell LLP
인용정보 피인용 횟수 : 45  인용 특허 : 18

초록

초록이 없습니다.

대표청구항

대표청구항이 없습니다.

이 특허에 인용된 특허 (18)

  1. Tsuchiva Kenichi (New Brighton MN) Kregness Glen R. (Minnetonka MN) Price deceased Ferris T. (late of Mayer MN by Robert Howe Price ; legal representative) Lucas Gary J. (Pine Springs MN), Apparatus and method for controlling exclusive access to portions of addressable memory in a multiprocessor system.
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  2. Chauvel, Gerard; Lasserre, Serge, Cache/smartcache with interruptible block prefetch.
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  3. Thaler Wolfgang J. ; Bertoni Jonathan L., Caching virtual memory locks.
    상세보기
  4. Ann Marie Maynard ; Brian Chase Twichell AU, Computer memory address translation system.
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  5. Welker Mark W. ; Thayer John S., DMA controller which can be controlled by host and local processors.
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  6. Ooi Yasushi (Tokyo JPX) Miki Yoshiyuki (Tokyo JPX), Data processor which efficiently accesses main memory and input/output devices.
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  7. Houldsworth, Richard J., Data processor with localized memory reclamation.
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  8. Dumarot Daniel P. (Washingtonville NY) Garcia Armando (Yorktown Heights NY), High-performance, multi-bank global memory card for multiprocessor systems.
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  9. Paul E. McKenney ; Kevin A. Closson ; Raghupathi Malige, Lingering locks with fairness control for multi-node computer systems.
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  10. Odnert Daryl (Boulder Creek CA) Santhanam Vatsa (Sunnyvale CA), Method and apparatus for compiling computer programs with interprocedural register allocation.
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  11. Dahlen Dennis J. (Rhinebeck NY), Method and apparatus for controlling access by a plurality of processors to a shared resource.
    상세보기
  12. Bryant Barbara J. (Clinton Corners NY) Garrison Glen E. (Wallkill NY), Method and apparatus for providing token controlled access to protected pages of memory.
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  13. Letwin James (King County WA), Method and operating system for executing programs in a multi-mode microprocessor.
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  14. Weir Andrew P. ; Friel Joseph T., Method and system for device virtualization based on an interrupt request in a DOS-based environment.
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  15. Brooks James E. ; Collins Robert R. ; Shiell Jonathan H., Microprocessor with circuits, systems, and methods for selectively bypassing external interrupts past the monitor progr.
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  16. Horne Stephen P. (Austin TX) Song Seungyoon (Austin TX), Processing system and method including lock buffer for controlling exclusive critical problem accesses by each processor.
    상세보기
  17. Earnshaw William E. (N. Lauderdale FL) McKinney Steven J. (Coral Springs FL), Semaphore memory to reduce common bus contention to global memory with localized semaphores in a multiprocessor system.
    상세보기
  18. Singhal, Ashok; Hagersten, Erik, System and method for accessing a shared computer resource using a lock featuring different spin speeds corresponding to multiple states.
    상세보기

이 특허를 인용한 특허 (45)

  1. Abdallah, Mohammad, Accelerated code optimizer for a multiengine microprocessor.
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  2. Abdallah, Mohammad A., Apparatus and method for processing an instruction matrix specifying parallel and dependent operations.
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  3. Abdallah, Mohammad A., Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer.
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  4. Arimilli,Ravi Kumar; Cargnoni,Robert Alan; Guthrie,Guy Lynn; Starke,William John, Cross partition sharing of state information.
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  5. Abdallah, Mohammad, Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines.
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  6. Abdallah, Mohammad, Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines.
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  7. Abdallah, Mohammad, Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines.
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  8. Abdallah, Mohammad, Global and local interconnect structure comprising routing matrix to support the execution of instruction sequences by a plurality of engines.
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  9. Abdallah, Mohammad, Interconnect system to support the execution of instruction sequences by a plurality of partitionable engines.
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  10. Day, Michael N.; Gschwind, Michael Karl; Nutter, Mark R.; Xenidis, James, Logical partitioning and virtualization in a heterogeneous architecture.
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  11. Abdallah, Mohammad, Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines.
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  12. Chappell, Robert S.; Faistl, John W.; Gartler, Hermann W.; Tucknott, Michael D.; Parthasarathy, Rajesh S.; Burns, David W., Method and apparatus for bus lock assistance.
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  13. Lent, Marianne C.; Silvers, Charles H., Method and system for persistent, recoverable user-level locks.
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  14. Abdallah, Mohammad, Method for dependency broadcasting through a block organized source view data structure.
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  15. Abdallah, Mohammad, Method for dependency broadcasting through a source organized source view data structure.
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  16. Abdallah, Mohammad, Method for emulating a guest centralized flag architecture by using a native distributed flag architecture.
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  17. Abdallah, Mohammad, Method for executing multithreaded instructions grouped into blocks.
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  18. Abdallah, Mohammad, Method for executing multithreaded instructions grouped into blocks.
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  19. Abdallah, Mohammad, Method for implementing a reduced size register view data structure in a microprocessor.
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  20. Abdallah, Mohammad A., Method for implementing a reduced size register view data structure in a microprocessor.
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  21. Abdallah, Mohammad, Method for performing dual dispatch of blocks and half blocks.
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  22. Abdallah, Mohammad, Method for performing dual dispatch of blocks and half blocks.
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  23. Abdallah, Mohammad, Method for populating a source view data structure by using register template snapshots.
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  24. Abdallah, Mohammad, Method for populating and instruction view data structure by using register template snapshots.
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  25. Abdallah, Mohammad, Method for populating register view data structure by using register template snapshots.
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  26. Michaud, Adrian; Clark, Roy E., Methods and apparatus for direct cache-line access to attached storage with cache.
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  27. Michaud, Adrian; Clark, Roy E.; Taylor, Kenneth J., Methods and apparatus for memory tier page cache with zero file.
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  28. Abdallah, Mohammad; Rao, Ravishankar; Avudaiyappan, Karthikeyan, Methods, systems and apparatus for predicting the way of a set associative cache.
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  29. Abdallah, Mohammad; Rao, Ravishankar; Avudaiyappan, Karthikeyan, Methods, systems and apparatus for predicting the way of a set associative cache.
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  30. Abdallah, Mohammad; Rao, Ravishankar; Avudaiyappan, Karthikeyan, Methods, systems and apparatus for predicting the way of a set associative cache.
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  31. Abdallah, Mohammad; Groen, Ankur; Gunadi, Erika; Singh, Mandeep; Rao, Ravishankar, Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation.
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  32. Cooney, Michael J.; Boboila, Marcela S.; DiPietro, Guido A., Prioritization for cache systems.
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  33. Bohizic, Theodore J.; Decker, Mark H.; Gyuris, Viktor S., Providing memory consistency in an emulated processing environment.
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  34. von Praun,Christoph; Choi,Jong Deok, Reader-initiated shared memory synchronization.
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  35. Abdallah, Mohammad, Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines.
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  36. Abdallah, Mohammad, Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines.
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  37. Abdallah, Mohammad, Single cycle multi-branch prediction including shadow cache for early far branch prediction.
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  38. Clark, Roy E.; Michaud, Adrian, System and method utilizing a cache free list and first and second page caches managed as a single cache in an exclusive manner.
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  39. Sugizaki, Go, System controller, information processing system, and access processing method.
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  40. Arimilli, Lakshminarayana B.; Arimilli, Ravi K.; Sinharoy, Balaram, Techniques for cache injection in a processor system.
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  41. Arimilli, Lakshminarayana Baba; Arimilli, Ravi K.; Joyner, Jody B.; Starke, William J., Techniques for cache injection in a processor system based on a shared state.
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  42. Arimilli, Lakshminarayana Baba; Arimilli, Ravi K.; Joyner, Jody B.; Starke, William J., Techniques for cache injection in a processor system from a remote node.
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  43. Arimilli, Lakshminarayana Baba; Arimilli, Ravi K.; Sinharoy, Balaram, Techniques for cache injection in a processor system responsive to a specific instruction sequence.
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  44. Arimilli, Lakshminarayana Baba; Arimilli, Ravi K.; Sinharoy, Balaram, Techniques for cache injection in a processor system using a cache injection instruction.
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  45. Arimilli, Lakshminarayana Baba; Arimilli, Ravi K.; Sinharoy, Balaram, Techniques for cache injection in a processor system with replacement policy position modification.
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