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Programmable integrated circuit providing efficient implementations of arithmetic functions 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-007/38
  • H03K-019/173
출원번호 US-0151915 (2005-06-14)
발명자 / 주소
  • Young,Steven P.
  • Bauer,Trevor J.
출원인 / 주소
  • Xilinx, Inc.
인용정보 피인용 횟수 : 42  인용 특허 : 23

초록

초록이 없습니다.

대표청구항

대표청구항이 없습니다.

이 특허에 인용된 특허 (23)

  1. Pedersen, Bruce, Automated implementation of non-arithmetic operators in an arithmetic logic cell.
    상세보기
  2. Chapman, Kenneth D.; Young, Steven P., Configurable logic block with and gate for efficient multiplication in FPGAS.
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  3. Young Steven P. ; Bapat Shekhar ; Chaudhary Kamal ; Bauer Trevor J. ; Iwanczuk Roman, Configurable logic element with ability to evaluate five and six input functions.
    상세보기
  4. Bernard J. New ; Ralph D. Wittig ; Sundararajarao Mohan, Configurable logic element with expander structures.
    상세보기
  5. Young Steven P. ; New Bernard J. ; Camilleri Nicolas John ; Bauer Trevor J. ; Bapat Shekhar ; Chaudhary Kamal ; Krishnamurthy Sridhar, Configurable logic element with fast feedback paths.
    상세보기
  6. Ralph D. Wittig ; Sundararajarao Mohan ; Bernard J. New, Configurable lookup table for programmable logic devices.
    상세보기
  7. Bauer Trevor J. ; Young Steven P., FPGA architecture with deep look-up table RAMs.
    상세보기
  8. Bauer Trevor J. ; Young Steven P., FPGA architecture with dual-port deep look-up table RAMS.
    상세보기
  9. Bauer Trevor J. ; Young Steven P., FPGA architecture with wide function multiplexers.
    상세보기
  10. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., FPGA configurable logic block with multi-purpose logic/memory circuit.
    상세보기
  11. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., FPGA configurable logic block with multi-purpose logic/memory circuit.
    상세보기
  12. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., FPGA configurable logic block with multi-purpose logic/memory circuit.
    상세보기
  13. Chaudhary Kamal, FPGA having logic element carry chains capable of generating wide XOR functions.
    상세보기
  14. Ralph D. Wittig ; Sundararajarao Mohan ; Bernard J. New, FPGA logic element with variable-length shift register capability.
    상세보기
  15. Trevor J. Bauer ; Steven P. Young ; Richard A. Carberry, FPGA lookup table with dual ended writes for ram and shift register modes.
    상세보기
  16. Young Steven P. ; Chaudhary Kamal ; Bauer Trevor J., FPGA repeatable interconnect structure with hierarchical interconnect lines.
    상세보기
  17. Nakaya, Shogo, Function block.
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  18. Ralph D. Wittig ; Sundararajarao Mohan ; Richard A. Carberry, Logic/memory circuit having a plurality of operating modes.
    상세보기
  19. New Bernard J., Look-ahead carry structure with homogeneous CLB structure and pitch larger than CLB pitch.
    상세보기
  20. Bauer Trevor J., Lookup tables which double as shift registers.
    상세보기
  21. Wittig Ralph D. ; Mohan Sundararajarao, Method for implementing large multiplexers with FPGA lookup tables.
    상세보기
  22. Chaudhary Kamal, Method for implementing priority encoders using FPGA carry logic.
    상세보기
  23. Bauer Trevor J. ; Newgard Bruce A. ; Allaire William E. ; Young Steven P., Structure for optionally cascading shift registers.
    상세보기

이 특허를 인용한 특허 (42)

  1. Ching, Alvin Y.; Wong, Jennifer; New, Bernard J.; Simkins, James M.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Architectural floorplan for a digital signal processing circuit.
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  2. Wong, Anna Wing Wah; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Simkins, James M.; Vadi, Vasisht Mantra; Schultz, David P., Arithmetic logic unit circuit.
    상세보기
  3. Taylor, Bradley L., Configurable arithmetic block and a method of implementing a configurable arithmetic block in a device having programmable logic.
    상세보기
  4. Taylor, Bradley L., Configurable arithmetic block and method of implementing arithmetic functions in a device having programmable logic.
    상세보기
  5. Katti, Romney R., Configurable reference circuit for logic gates.
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  6. Yehia, Sami; Flautner, Krisztian, Data processing apparatus and method for accelerating execution of subgraphs.
    상세보기
  7. Taylor, Bradley L., Device having programmable logic for implementing arithmetic functions.
    상세보기
  8. New, Bernard J.; Vadi, Vasisht Mantra; Wong, Jennifer; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M., Digital signal processing block having a wide multiplexer.
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  9. Simkins, James M.; Ching, Alvin Y.; Thendean, John M.; Vadi, Vasisht M.; Poon, Chi Fung; Rab, Muhammad Asim, Digital signal processing block with preadder stage.
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  10. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having a SIMD circuit.
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  11. Vadi, Vasisht Mantra; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M., Digital signal processing circuit having a pattern circuit for determining termination conditions.
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  12. Vadi, Vasisht Mantra; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M., Digital signal processing circuit having a pattern detector circuit.
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  13. New, Bernard J.; Wong, Jennifer; Simkins, James M.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having a pattern detector circuit for convergent rounding.
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  14. Simkins, James M.; Thendean, John M.; Vadi, Vasisht Mantra; New, Bernard J.; Wong, Jennifer; Wong, Anna Wing Wah; Ching, Alvin Y., Digital signal processing circuit having a pre-adder circuit.
    상세보기
  15. Thendean, John M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Simkins, James M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having an adder circuit with carry-outs.
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  16. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having input register blocks.
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  17. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra; Schultz, David P., Digital signal processing element having an arithmetic logic unit.
    상세보기
  18. Kiel,Steven Lee; Krening,Douglas Norman; Lehman,Lark Edward; Schneiderwind,Michael Joseph, Dynamically configurable logic gate using a non-linear element.
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  19. Hecht, Volker; Derevlean, Marcel; Greene, Jonathan, Fast carry lookahead circuits.
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  20. Plants, William C., Flexible carry scheme for field programmable gate arrays.
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  21. Plants, William C., Flexible carry scheme for field programmable gate arrays.
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  22. Camarota, Rafael C., Flexible sized die for use in multi-die integrated circuit.
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  23. Fan, Yuezhen; Thorne, Eric J.; Li, Xiao-Yu; O'Rourke, Glenn; Trimberger, Stephen M., Increased usable programmable device dice.
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  24. Cashman, David; Lewis, David; Manohararajah, Valavan, Integrated circuits with multi-stage logic regions.
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  25. Dewan, Hitanshu, Logic entity with two outputs for efficient adder and other macro implementations.
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  26. Feng, Wenyi; Greene, Jonathan, Logic module including versatile adder for FPGA.
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  27. Katti, Romney R., Magnetic logic gate.
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  28. Katti, Romney R., Magnetic logic gate.
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  29. Katti, Romney R., Magnetic logic gate.
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  30. Wendling, Xavier; Simkins, James M., Method of and circuit for implementing a filter in an integrated circuit.
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  31. Bauer, Trevor J.; Lindholm, Jeffrey V.; Goetting, F. Erich; Talley, Bruce E.; Tanikella, Ramakrishna K.; Young, Steven P., Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies.
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  32. Bauer,Trevor J.; Lindholm,Jeffrey V.; Goetting,F. Erich; Talley,Bruce E.; Tanikella,Ramakrishna K.; Young,Steven P., Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies.
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  33. Goetting,F. Erich; Bauer,Trevor J.; McGuire,Patrick J.; Talley,Bruce E.; Wu,Paul Ying Fung; Young,Steven P., Methods of providing a family of related integrated circuits of different sizes.
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  34. Pang,Raymond C.; Bauer,Trevor J.; Goetting,F. Erich; Talley,Bruce E.; Young,Steven P., Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes.
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  35. Camarota, Rafael C., Monolithic integrated circuit die having modular die regions stitched together.
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  36. Vashishta, Tarun Kumar; Agarwal, Priyanka, N-bit constant adder/subtractor.
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  37. Hisamura, Toshiyuki, Oversized interposer.
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  38. Camarota, Rafael C., Oversized interposer formed from a multi-pattern region mask.
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  39. Katti, Romney R., Reduced switching-energy magnetic elements.
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  40. Hisamura, Toshiyuki, Single mask set used for interposer fabrication of multiple products.
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  41. Walters, III, Eugene George, Techniques and devices for performing arithmetic.
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  42. Young,Steven P.; Bauer,Trevor J.; Goetting,F. Erich; Lamarche,P. Hugo; McGuire,Patrick J.; Oh,Kwansuhk; Pang,Raymond C.; Talley,Bruce E.; Wu,Paul Ying Fung, Yield-enhancing methods of providing a family of scaled integrated circuits.
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