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Software-to-hardware compiler 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/45
  • G06F-017/50
출원번호 US-0924272 (2001-08-07)
발명자 / 주소
  • Metzgen,Paul
출원인 / 주소
  • Altera Corporation
대리인 / 주소
    Fish & Neave IP Group of Ropes & Gray LLP
인용정보 피인용 횟수 : 14  인용 특허 : 31

초록

초록이 없습니다.

대표청구항

대표청구항이 없습니다.

이 특허에 인용된 특허 (31)

  1. Earl A. Killian ; Ricardo E. Gonzalez ; Ashish B. Dixit ; Monica Lam ; Walter D. Lichtenstein ; Christopher Rowen ; John C. Ruttenberg ; Robert P. Wilson ; Albert Ren-Rui Wang ; Dror Eliezer, Automated processor generation system for designing a configurable processor and method for the same.
  2. Shail Aditya Gupta ; B. Ramakrishna Rau ; Richard C. Johnson ; Michael S. Schlansker, Automatic design of VLIW instruction formats.
  3. Sharrit Paul ; Campini Edoardo ; Cornils Curtis L., Communicator having reconfigurable resources.
  4. Alkalaj Leon ; Fang Wai-Chi ; Newell Michael A., Electronic processing and control system with programmable hardware.
  5. Chun Robert K. (Fullerton CA), Expert system compilation method.
  6. Southgate Timothy James, FPGA based configurable CPU additionally including second programmable section for implementation of custom hardware su.
  7. Casselman Steven Mark (Reseda CA), FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in.
  8. Razdan Rahul ; Smith Michael D., Hardware extraction technique for programmable reduced instruction set computers.
  9. Kean Thomas A. (Edinburgh GB6), Hierarchically connectable configurable cellular array.
  10. Wong Dale ; Phillips Christopher E. ; Cooke Laurence H., Integrated processor and programmable data path chip for reconfigurable computing.
  11. Edwards, Stephen G.; Harris, Jonathan Craig; Jensen, James E.; Kollegger, Andreas Benno; Miller, Ian David; Sunderland Schanck, Christopher Robert; Davis, Donald J., Means and method for compiling high level software languages into algorithmically equivalent hardware representations.
  12. Rostoker Michael D. (Boulder Creek CA) Dangelo Carlos (Los Gatos CA) Mintz Doron (Sunnyvale CA), Method and system for creating and validating low level description of electronic design from higher level, behavior-ori.
  13. Cooke Laurence H. ; Phillips Christopher E. ; Wong Dale, Method for compiling high level programming languages into an integrated processor with reconfigurable logic.
  14. Sven Wuytack BE; Francky Catthoor BE; Hugo De Man BE, Method for determining a storage bandwidth optimized memory organization of an essentially digital device.
  15. Jain Prem P., Method for graphically representing a digital device as a behavioral description with data and control flow elements, and for converting the behavioral description to a structural description.
  16. Nakai Masaaki (Kawachinagano JPX), One-chip microcomputer including a programmable logic array for interrupt control.
  17. Taylor Brad (Oakland CA), Pld connector for module having configuration of either first PLD or second PLD and reconfigurable bus for communication.
  18. Robinson Jeffrey I. (New Fairfield CT), Programmable integrated circuit using topological and parametric data to selectively connect and configure different hig.
  19. Kean Thomas A.,GB6, Programmable switch for FPGA input/output signals.
  20. Smith Stephen J., Reconfigurable computer architecture using programmable logic devices.
  21. Smith Stephen J., Reconfigurable computer architecture using programmable logic devices.
  22. Madurawe Raminda (Sunnyvale CA), Reconfigurable programmable logic device having static and non-volatile memory.
  23. Koichi Sato JP; Lcu Semeria ; Giovanni De Micheli, Resolution of dynamic memory allocation/deallocation and pointers.
  24. Anderson Forrest (P.O. Box 1400 Bernalillo NM 87004), Single pulse imaging device.
  25. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian Keith; Butler, Cary Paul; Mihal, Andrew, System and method for configuring a programmable hardware instrument to perform measurement functions utilizing estimation of the hardware implentation and management of hardware resources.
  26. Kodosky Jeffrey L. ; Andrade Hugo ; Odom Brian K. ; Butler Cary P., System and method for configuring an instrument to perform measurement functions utilizing conversion of graphical programs into hardware implementations.
  27. Lacey Steve,GB2, System and method for parsing and executing a single instruction stream using a plurality of tightly coupled parsing and.
  28. Panchul Yuri V. ; Soderman Donald A. ; Coleman Denis R., System for converting hardware designs in high-level programming language to hardware implementations.
  29. Ashar, Pranav; Raghunathan, Anand; Bhattacharya, Subhrajit; Gupta, Aarti, Verification of scheduling in the presence of loops using uninterpreted symbolic simulation.
  30. Agarwal Anant ; Babb Jonathan ; Tessier Russell, Virtual interconnections for reconfigurable logic systems.
  31. Kolchinsky Alexander (48 Gray Rd. Andover MA 01810), Virtual processor module including a reconfigurable programmable matrix.

이 특허를 인용한 특허 (14)

  1. Schumacher, Paul R.; Turney, Robert D.; Paluszkiewicz, Mark; Sundararajan, Prasanna; Blodget, Brandon J., Concealed, non-intrusive watermarks for configuration bitstreams.
  2. Chen, Doris Tzu-Lang; Singh, Deshanand, Configuring a programmable device using high-level language.
  3. Chen, Doris Tzu-Lang; Singh, Deshanand, Configuring a programmable device using high-level language.
  4. Wakabayashi, Kazutoshi, Description processing device, description processing method, and recording medium.
  5. Ritzau, Tobias; Moller, Rickard, Method and software for optimising the positioning of software functions in a memory.
  6. Ebcioglu, Kemal; Kultursay, Emre, Method and system for converting a single-threaded software program into an application-specific supercomputer.
  7. Ebcioglu, Kemal; Kultursay, Emre, Method and system for converting a single-threaded software program into an application-specific supercomputer.
  8. Ebcioglu, Kemal; Kultursay, Emre; Kandemir, Mahmut Taylan, Method and system for converting a single-threaded software program into an application-specific supercomputer.
  9. Patterson,Cameron D.; Sundararajan,Prasanna; Blodget,Brandon J.; McMillan,Scott P., Method and system for identifying essential configuration bits.
  10. Kavipurapu, Gautam, Scheduler for a fine grained graph processor.
  11. Boden, Kurt Thomas, Semaphore soft and hard hybrid architecture.
  12. Metzgen, Paul, Software-to-hardware compiler.
  13. Bendert, Edward J.; Howland, Melissa K.; Shultz, Steven, System, method and program product for control of sequencing of data processing by different programs.
  14. Young, Joshua; Turney, Dianne J., Systems and methods for reconfigurable computing.
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