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Operational time extension 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/173
  • H03K-019/177
  • G06F-007/38
  • H01L-025/00
출원번호 US-0082200 (2005-03-15)
발명자 / 주소
  • Rohe,Andre
  • Teig,Steven
  • Schmit,Herman
  • Redgrave,Jason
  • Caldwell,Andrew
출원인 / 주소
  • Rohe,Andre
  • Teig,Steven
  • Schmit,Herman
  • Redgrave,Jason
  • Caldwell,Andrew
대리인 / 주소
    Adeli Law Group
인용정보 피인용 횟수 : 55  인용 특허 : 61

초록

초록이 없습니다.

대표청구항

대표청구항이 없습니다.

이 특허에 인용된 특허 (61)

  1. Lo, William, Circuit for reducing pin count of a semiconductor chip and method for configuring the chip.
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  2. Cliff Richard G., Coarse-grained look-up table architecture.
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  3. Kaviani Alireza S.,CAXITX M5R 2R5 ; Brown Steven D.,CAXITX M4R 2A3, Computational field programmable architecture.
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  4. Snyder, Warren, Configuring digital functions in a digital configurable macro architecture.
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  5. Scalera Stephen M. ; Vazquez Jose R., Context switchable field programmable gate array with public-private addressable sharing of intermediate data.
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  6. Iadanza Joseph A., Cross-coupled bitline segments for generalized data propagation.
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  7. Rajsuman Rochit, Domino scan architecture and domino scan flip-flop for the testing of domino and hybrid CMOS circuits.
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  8. Altaf, K. Risa, Driver circuitry for programmable logic devices with hierarchical interconnection resources.
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  9. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., FPGA configurable logic block with multi-purpose logic/memory circuit.
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  10. James L. Burnham ; Gary R. Lawman ; Joseph D. Linoff, FPGA customizable to accept selected macros.
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  11. Chaudhary Kamal, FPGA having logic element carry chains capable of generating wide XOR functions.
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  12. Carberry, Richard A.; Young, Steven P.; Bauer, Trevor J., FPGA lookup table with speed read decoder.
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  13. Pi, Tao; Crotty, Patrick J., FPGA lookup table with transmission gate structure for reliable low-voltage operation.
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  14. Young Steven P. ; Chaudhary Kamal ; Bauer Trevor J., FPGA repeatable interconnect structure with hierarchical interconnect lines.
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  15. Kean Thomas A.,GB6 ITX EH88JQ ; Wilkie William A.,GB6 ITX EH106AP, FPGA with parallel and serial user interfaces.
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  16. Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray, Field programmable memory array.
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  17. Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Seidel Victor Paul ; Zittritsch Terrance John, Field programmable memory array.
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  18. Iadanza Joseph Andrew ; Kilmoyer Ralph David ; Laramie Michael Joseph ; Seidel Victor Paul ; Zittritsch Terrance John, Field programmable memory array.
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  19. Bennett David Wayne (Louisville CO) Dellinger Eric Ford (Boulder CO) Manaker ; Jr. Walter A. (Boulder CO) Stern Carl M. (Boulder CO) Troxel William R. (Longmont CO) Young Jay Thomas (Louisville CO), Frequency driven layout and method for field programmable gate arrays.
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  20. Southgate Timothy J. ; Wenzler Michael, Graphic editor for block diagram level design of circuits.
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  21. Rostoker Michael D. ; Koford James S. ; Scepanovic Ranko ; Jones Edwin R. ; Padmanahben Gobi R. ; Kapoor Ashok K. ; Kudryavtsev Valeriy B.,RUX ; Andreev Alexander E.,RUX ; Aleshin Stanislav V.,RUX ; , Hexagonal field programmable gate array architecture.
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  22. Laramie Michael J., Interconnect structure between heterogeneous core regions in a programmable array.
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  23. Goetting F. Erich (Cupertino CA) Trimberger Stephen M. (San Jose CA), Logic cell for field programmable gate array having optional internal feedback and optional cascade.
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  24. New Bernard J. (Los Gatos CA), Logic structure and circuit for fast carry.
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  25. Dike, Charles E., Long setup flip-flop for improved synchronization capabilities.
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  26. Norman Kevin A. ; Patel Rakesh H. ; Sample Stephen P. ; Butts Michael R., Look-up table based logic element with complete permutability of the inputs to the secondary signals.
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  27. Chiang David (Saratoga CA) Lee Napoleon W. (Fremont CA) Ho Thomas Y. (Milpitas CA) Harrison David A. (Cupertino CA) Kucharewski ; Jr. Nicholas (Pleasanton CA) Seltzer Jeffrey H. (San Jose CA), Macrocell with product-term cascade and improved flip flop utilization.
    상세보기
  28. Clinton Kim P. N. ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Seidel Victor Paul ; Zittritsch Terrance John, Memory cells for field programmable memory array.
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  29. Larsen Wendell Ray (Essex Junction VT) Keyser Frank Ray (Colchester VT) Worth Brian A. (Milton VT), Memory mapping method and apparatus to fold sparsely populated structures into densely populated memory columns or rows.
    상세보기
  30. Gould Scott W. (So. Burlington VT), Method and system for enhanced drive in programmmable gate arrays.
    상세보기
  31. Fuller Christine Marie ; Hartman Steven Paul ; Millham Eric Ernest, Method and system for optimizing a critical path in a field programmable gate array configuration.
    상세보기
  32. Craft David John ; Gould Scott Whitney ; Keyser ; III Frank Ray ; Worth Brian, Method and system for programming a gate array using a compressed configuration bit stream.
    상세보기
  33. Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable function within a chip to enable configurable I/O signal timing characteristics.
    상세보기
  34. Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable function within a standard cell chip for repair of logic circuits.
    상세보기
  35. Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable interconnect within an ASIC for configuring the ASIC.
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  36. Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of an embedded field programmable gate array interconnect for flexible I/O connectivity.
    상세보기
  37. Kong, Raymond; Anderson, Jason H., Method for computing and using future costing data in signal routing.
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  38. Baxter, Glenn A., Method for controlling timing in reduced programmable logic devices.
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  39. Glenn A. Baxter, Method for converting programmable logic devices into standard cell devices.
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  40. Trimberger, Stephen M., Method for making large-scale ASIC using pre-engineered long distance routing structure.
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  41. Baxter, Glenn A., Method for managing database models for reduced programmable logic device components.
    상세보기
  42. Trimberger Stephen M. (San Jose CA), Method for programming an FPLD using a library-based technology mapping algorithm.
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  43. Trimberger Stephen M. (San Jose CA), Method for programming an FPLD using a library-based technology mapping algorithm.
    상세보기
  44. Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Zittritsch Terrance John, Method of operating a field programmable memory array with a field programmable gate array.
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  45. Chaudhary Kamal ; Nag Sudip K., Post-placement residual overlap removal method for core-based PLD programming process.
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  46. Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Zittritsch Terrance John, Programmable address decoder for field programmable memory array.
    상세보기
  47. Gould Scott Whitney ; Keyser ; III Frank Ray ; Larsen Wendell Ray ; Worth Brian Allen, Programmable array interconnect latch.
    상세보기
  48. Clinton Kim P. N. (Essex Junction VT) Gould Scott W. (South Burlington VT) Hartman Steven P. (Jericho VT) Iadanza Joseph A. (Hinesburg VT) Keyser ; III Frank R. (Colchester VT) Millham Eric E. (St. G, Programmable array interconnect network.
    상세보기
  49. Iadanza Joseph Andrew ; Keyser ; III Frank Ray, Programmable bit line drive modes for memory arrays.
    상세보기
  50. El Gamal Abbas A. (Palo Alto CA) El-Ayat Khaled A. (Cupertino CA) Greene Jonathan W. (Palo Alto CA) Guo Ta-Pen R. (Cupertino CA) Reyneri Justin M. (Los Altos CA), Programmable interconnect architecture.
    상세보기
  51. Baxter, Glenn A., Programmable logic device structures in standard cell devices.
    상세보기
  52. Iadanza Joseph Andrew, Programmable parity checking and comparison circuit.
    상세보기
  53. Iadanza Joseph Andrew, Programmable read ports and write ports for I/O buses in a field programmable memory array.
    상세보기
  54. Darling, Roy D.; Shimanek, Schuyler E.; Davies, Jr., Thomas J., Programming on-the-fly (OTF).
    상세보기
  55. New Bernard J. ; Johnson Robert Anders ; Wittig Ralph ; Mohan Sundararajarao, Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM.
    상세보기
  56. Ochotta Emil S. ; Wieland Douglas P., Routing architecture using a direct connect routing mesh.
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  57. Eric R. Keller ; Steven A. Guccione ; Delon Levi, Run-time routing for programmable logic devices.
    상세보기
  58. Clinton Kim P. N. ; Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Kilmoyer Ralph David ; Laramie Michael Joseph ; Seidel Victor Paul ; Zittritsch Terrance John, Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array.
    상세보기
  59. Iadanza Joseph Andrew (Hinesburg VT), System and method for dynamically reconfiguring a programmable gate array.
    상세보기
  60. Gould Scott Whitney (Burlington VT), System for enhanced drive in programmable gate arrays.
    상세보기
  61. Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Kilmoyer Ralph David ; Laramie Michael Joseph, System for implementing write, initialization, and reset in a memory array using a single cell write port.
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이 특허를 인용한 특허 (55)

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  2. Schmit, Herman; Huang, Randy Renfu, Configurable IC having a routing fabric with storage elements.
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  3. Teig, Steven, Configurable IC having a routing fabric with storage elements.
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  4. Teig, Steven; Schmit, Herman; Huang, Randy Renfu, Configurable IC having a routing fabric with storage elements.
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  5. Teig, Steven; Schmit, Herman; Huang, Randy Renfu, Configurable IC having a routing fabric with storage elements.
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  6. Teig, Steven; Schmit, Herman; Redgrave, Jason, Configurable IC having a routing fabric with storage elements.
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  7. Teig, Steven; Redgrave, Jason, Configurable IC with error detection and correction circuitry.
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  8. Teig, Steven; Schmit, Herman; Redgrave, Jason; Chandra, Vikas, Configurable IC with interconnect circuits that also perform storage operations.
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  9. Teig, Steven; Caldwell, Andrew; Redgrave, Jason, Configurable ICs that conditionally transition through configuration data sets.
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  10. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Configurable circuits, IC's, and systems.
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  11. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Configurable circuits, IC's, and systems.
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  12. Teig, Steven; Redgrave, Jason; Horel, Timothy, Configurable integrated circuit with error correcting circuitry.
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  13. Voogel, Martin; Teig, Steven; Chanack, Thomas S.; Caldwell, Andrew; Ko, Jung; Chandler, Trevis, Configurable storage elements.
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  14. Chandler, Trevis; Redgrave, Jason; Voogel, Martin, Configuration context switcher.
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  15. Chandler, Trevis; Redgrave, Jason; Voogel, Martin, Configuration context switcher.
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  16. Chandler, Trevis; Entjer, Joe; Voogel, Martin; Redgrave, Jason, Configuration context switcher with a clocked storage element.
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  17. Chandler, Trevis; Entjer, Joe; Voogel, Martin; Redgrave, Jason, Configuration context switcher with a clocked storage element.
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  18. Chandler, Trevis; Entjer, Joe; Voogel, Martin; Redgrave, Jason, Configuration context switcher with a clocked storage element.
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  19. Voogel, Martin; Redgrave, Jason; Chandler, Trevis, Configuration context switcher with a latch.
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  20. Voogel, Martin; Redgrave, Jason; Chandler, Trevis, Configuration context switcher with a latch.
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  21. Redgrave, Jason; Voogel, Martin; Teig, Steven, Controllable storage elements for an IC.
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  22. Redgrave, Jason; Voogel, Martin; Teig, Steven, Controllable storage elements for an IC.
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  23. Caldwell, Andrew; Teig, Steven, Decision modules.
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  24. Mihal, Andrew C.; Teig, Steven, Detailed placement with search and repair.
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  25. Zhang, Wei; Jha, Niraj K.; Shang, Li, Hybrid nanotube/CMOS dynamically reconfigurable architecture and an integrated design optimization method and system therefor.
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  26. Zhang, Wei; Jha, Niraj K.; Shang, Li, Hybrid nanotube/CMOS dynamically reconfigurable architecture and system therefore.
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  27. Pugh, Daniel J.; Caldwell, Andrew, IC that efficiently replicates a function to save logic and routing resources.
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  28. Redgrave, Jason, Method and apparatus for accessing stored data in a reconfigurable IC.
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  29. Caldwell, Andrew; Teig, Steven, Method and apparatus for function decomposition.
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  30. Redgrave, Jason; Caldwell, Andrew; Teig, Steven, Method and apparatus for performing an operation with a plurality of sub-operations in a configurable IC.
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  31. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Method of mapping a user design defined for a user design cycle to an IC with multiple sub-cycle reconfigurable circuits.
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  32. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Non-sequentially configurable IC.
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  33. Rohe, Andre; Teig, Steven, Operational cycle assignment in a configurable IC.
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  34. Rohe, Andre; Teig, Steven, Operational cycle assignment in a configurable IC.
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  35. Rohe, Andre; Teig, Steven, Operational cycle assignment in a configurable IC.
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  36. Rohe, Andre; Teig, Steven, Operational cycle assignment in a configurable IC.
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  37. Rohe, Andre; Teig, Steven; Schmit, Herman; Redgrave, Jason; Caldwell, Andrew, Operational time extension.
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  38. Rohe, Andre; Teig, Steven; Schmit, Herman; Redgrave, Jason; Caldwell, Andrew, Operational time extension.
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  39. Rohe, Andre; Teig, Steven; Schmit, Herman; Redgrave, Jason; Caldwell, Andrew, Operational time extension.
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  40. Voogel, Martin; Redgrave, Jason; Chandler, Trevis, Reading configuration data from internal storage node of configuration storage circuit.
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  45. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.
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  46. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.
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  47. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.
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  48. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.
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  49. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.
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