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Method of using a mask programmed key to securely configure a field programmable gate array 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H04L-009/32
출원번호 US-0780681 (2001-02-08)
우선권정보 GB-0002829.0(2000-02-09)
발명자 / 주소
  • Kean,Thomas A.
출원인 / 주소
  • Algotronix, Ltd.
대리인 / 주소
    Orrick, Herrington & Sutcliffe LLP
인용정보 피인용 횟수 : 27  인용 특허 : 58

초록

초록이 없습니다.

대표청구항

대표청구항이 없습니다.

이 특허에 인용된 특허 (58)

  1. Redman Scott ; Mak Dennis ; Terrill Richard, Access restriction to circuit designs.
  2. Janssen John Jerome ; Olsen Steven J., Apparatus and method for securing electronic information in a wireless communication device.
  3. Bright Michael W. ; Fuchs Kenneth Carl ; Marquardt Kelly Jo, Apparatus and method of reading a program into a processor.
  4. Roselli, Leonard, Arrangement for reading an absolute position encoder for determining the operating position of a break handle.
  5. Sehr Richard P., Card system and methods utilizing collector cards.
  6. Hoffman Jeffrey D., Cipher core in a content protection system.
  7. Johnstone ; Richard, Computer software security system.
  8. Kean Thomas A.,GBX, Configurable cellular array.
  9. Trimberger Stephen M., Configurable electronic device which is compatible with a configuration bitstream of a prior generation configurable ele.
  10. Rangasayee Krishna, Configuration eprom with programmable logic.
  11. Erickson Charles R., Configuration stream encryption.
  12. Lawman Gary R., Configuring an FPGA using embedded memory.
  13. Best Robert M. (16016 9th Ave. NE. Seattle WA 98155), Crypto microprocessor that executes enciphered programs.
  14. Plants, William C., Cyclic redundancy checking of a field programmable gate array having a SRAM memory architecture.
  15. Lai Yi-Sern,TWX ; Chuang I-Yao,TWX ; Chiou Bor-Wen,TWX ; Yang Chin-Ning,TWX, DES cipher processor for full duplex interleaving encryption/decryption service.
  16. Austin Kenneth (Northwich GBX), Data security arrangements for semiconductor programmable devices.
  17. Klein, Dean A., Data security for digital data storage.
  18. Lawman Gary R., Decoder structure and method for FPGA configuration.
  19. David C. Wentker ; Klaus P. Gungl DE, Delegated management of smart card applications.
  20. Hampson Bradford E. (Framingham MA), Digital computer system for executing encrypted programs.
  21. Kocher, Paul C.; Jaffe, Joshua M.; Jun, Benjamin C., Digital content protection method and apparatus.
  22. Cohen Joshua L. ; Dean Cecil A. ; du Breuil Thomas L. ; Heer Daniel Nelson ; Maher David P. ; Poteat Vance Eugene ; Rance Robert John, Electronic identifiers for network terminal devices.
  23. Chojnacki, Robert, Encryption method for distribution of data.
  24. Erickson Charles R. ; Tavana Danesh ; Holen Victor A., Encryption of configuration stream.
  25. Burnham James L. ; Lawman Gary R. ; Linoff Joseph D., FPGA customizable to accept selected macros.
  26. Paul Jeffrey Garnett GB, Field programmable gate arrays.
  27. Yearsley Gyle (Boise ID) Richards Grant (Meridian ID), Firmware encryption for microprocessor/microcomputer.
  28. Karp Alan H. (Palo Alto CA), Hardware assist for protecting PC software.
  29. Erickson Brian D., Integrated circuit packaged for receiving another integrated circuit.
  30. Loukianov, Dmitrii, Method and an apparatus for secure register access in electronic device.
  31. Pastor Jose (Westport CT) Barton Maya R. (Ridgefield CT), Method and apparatus for generating encryption/decryption key.
  32. Trimberger, Stephen M., Method and apparatus for protecting proprietary configuration data for programmable logic devices.
  33. Sung Chiakang ; Wang Bonnie I., Method and apparatus for securing programming data of a programmable logic device.
  34. Sung Chiakang ; Wang Bonnie I., Method and apparatus for securing programming data of programmable logic device.
  35. Lawman Gary R., Method for generating a secure macro element of a design for a programmable IC.
  36. Wong Albert C. K. (Golden Valley MN) Jurewicz Romuald M. (St. Louis Park MN) McCormack Michael D. (Robbinsdale MN), Method of determining the condition of a back-up battery for a real time clock.
  37. Choi Byeng-Sun,KRX, Multi-bit memory device having error check and correction circuit and method for checking and correcting data errors therein.
  38. Rao Kameswara K. ; Voogel Martin L., Non-volatile storage for standard CMOS integrated circuits.
  39. Chiu Ming-Yee (Mt. Laurel NJ), On-chip microprocessor instruction decoder having hardware for selectively bypassing on-chip circuitry used to decipher.
  40. Curd Derek R. ; Jacobson Neil G. ; Diba Sholeh ; Lee Napoleon W. ; Ku Wei-Yi ; Rao Kameswara K., Overridable data protection mechanism for PLDs.
  41. Lawman Gary R., PROM with built-in JTAG capability for configuring FPGAs.
  42. Johnson William Cedric ; Marx Donald L., Personal access management systems.
  43. Thiriet Fabien P. (Orleans FRX), Process for protecting components of smart or chip cards from fraudulent use.
  44. Hazard, Michel, Process for storage and use of sensitive information in a security module and the associated security module.
  45. Chiang David (Saratoga CA) Ho Thomas Y. (Milpitas CA) Ku Wei-Yi (Cupertino CA) Simmons George H. (Sunnyvale CA) Barker Robert W. (San Jose CA), Programmable logic device having security elements located amongst configuration bit location to prevent unauthorized re.
  46. Walter Paul Alan ; McGrogan ; Jr. Ellwood Patrick ; Kleidermacher Mike, Programmable telecommunications security module for key encryption adaptable for tokenless use.
  47. Stefik, Mark J.; Pirolli, Peter L. T., Repository with security class and method for use thereof.
  48. Matyas, Jr., Stephen Michael; Peyravian, Mohammad; Roginsky, Allen Leonid; Zunic, Nevenko, Secure data storage and retrieval with key management and user authentication.
  49. Candelore Brant ; Sprunk Eric, Secure processor with external memory using block chaining and block re-ordering.
  50. Apland James M. ; Eaton David D. ; Chan Andrew K., Security antifuse that prevents readout of some but not other information from a programmed field programmable gate arr.
  51. Nemoto Masahisa (Tokyo JPX), Semiconductor integrated circuit device having main power terminal and backup power terminal independently of each other.
  52. Gaffney, Jr., John E., Software cryptographic apparatus and method.
  53. Curran Kevin G. (Sudbury MA) Golson Steven E. (Wayland MA) Rode Christian S. (Cambridge MA), Software protection methods and apparatus.
  54. Buer Mark Leonard, Standard cell ring oscillator of a non-deterministic randomizer circuit.
  55. Kelem Steven H. ; Burnham James L., System and method for PLD bitstream encryption.
  56. Hair, Arthur R., System and method for manipulating a computer file and/or program.
  57. Hartman ; Jr. Robert C. (Woodside CA), System for seamless processing of encrypted and non-encrypted data and instructions.
  58. Guttag Karl M. (Houston TX), Use of implant process for programming ROM type processor for encryption.

이 특허를 인용한 특허 (27)

  1. Pinder, Howard G., Client control through content key format.
  2. Trimberger, Stephen M., Copy protection without non-volatile memory.
  3. Trimberger, Stephen M., Deterring reverse engineering.
  4. Donlin, Adam P.; Trimberger, Stephen M., Evolved circuits for bitstream protection.
  5. Luzzi, Raimondo; Bucci, Marco, Integrated circuit and method for preventing an unauthorized access to a digital value.
  6. Trimberger, Stephen M., Intellectual property core protection for integrated circuits.
  7. Walmsley, Simon Robert, Key transportation.
  8. Simkins, James M., Method and system for maintaining the security of design information.
  9. Simkins, James M., Method and system for maintaining the security of design information.
  10. Donlin, Adam P.; Sundararajan, Prasanna; New, Bernard J., Method and system for secure exchange of IP cores.
  11. Nelson,Michael D., Method for storing and shipping programmable ASSP devices.
  12. Trimberger, Stephen M., Methods of enabling the use of a defective programmable device.
  13. Trimberger, Stephen M., Methods of enabling the validation of an integrated circuit adapted to receive one of a plurality of configuration bitstreams.
  14. Trimberger, Stephen M., Methods of intrusion detection and prevention in secure programmable logic devices.
  15. Trimberger, Stephen M.; Ehteshami, Babak, Methods of using one of a plurality of configuration bitstreams for an integrated circuit.
  16. Jackson Pulver, Mark; Walmsley, Simon Robert; Sheahan, John Robert; Webb, Michael John, Print engine controller employing accumulative correction factor in pagewidth printhead.
  17. Silverbrook, Kia; Walmsley, Simon Robert; Sheahan, John Robert; Jackson Pulver, Mark; Webb, Michael John, Printer having printhead with multiple controllers.
  18. Walmsley, Simon Robert; Jackson Pulver, Mark; Sheahan, John Robert; Webb, Michael John; Silverbrook, Kia, Printhead having controlled nozzle firing grouping.
  19. Sheahan, John Robert; Silverbrook, Kia; Jackson Pulver, Mark; Webb, Michael John; Walmsley, Simon Robert, Printhead integrated circuit with thermally sensing heater elements.
  20. McLean, Ian; Keating, Stephen Mark, Programmable logic device.
  21. Trimberger, Stephen M., Protecting a design for an integrated circuit using a unique identifier.
  22. Walmsley, Simon Robert, Resource entity using resource request entity for verification.
  23. Donlin, Adam P.; Sundararajan, Prasanna; New, Bernard J., Secure exchange of IP cores.
  24. Lewis, James M.; Haddock, Joey R.; Walther, Dane R., Self-modifying FPGA for anti-tamper applications.
  25. Lewis, James M.; Haddock, Joey R.; Walther, Dane R., Self-modifying FPGA for anti-tamper applications.
  26. Trimberger, Stephen M.; Lesea, Austin H., Unique identifier derived from an intrinsic characteristic of an integrated circuit.
  27. Walmsley, Simon Robert, Use of variant and base keys with three or more entities.
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