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Chip on board and heat sink attachment methods 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/02
출원번호 US-0624332 (2003-07-22)
발명자 / 주소
  • Hembree,David R.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    TraskBritt
인용정보 피인용 횟수 : 2  인용 특허 : 133

초록

초록이 없습니다.

대표청구항

대표청구항이 없습니다.

이 특허에 인용된 특허 (133)

  1. Toy Hilton T. ; Edwards David L. ; Shih Da-Yuan ; Giri Ajay P., Adhesion promoting layer for bonding polymeric adhesive to metal and a heat sink assembly using same.
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  66. Lamson Michael A. (Westminster TX) Heinen Katherine G. (Dallas TX), Method for making a balanced capacitance lead frame for integrated circuits having a power bus and dummy leads.
  67. Bigler Charles G. (Austin TX) Casto James J. (Austin TX) McShane Michael B. (Austin TX) Afshar David D. (Austin TX), Method for making a lead-on-chip semiconductor device having peripheral bond pads.
  68. Fujii Hiroyuki (Osaka JPX) Tateno Kenichi (Shiga JPX) Nishikawa Mikio (Kyoto JPX), Method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor.
  69. Mancke Ralph Gustavus (Bethlehem PA) Soos Nicholas Alec (Macungie PA), Method for removal of elastomeric silicone coatings from integrated circuits.
  70. Heiss ; Jr. John Herbert (Bethlehem PA) Schoen Joel Mark (Freehold NJ), Method for selective encapsulation.
  71. Rostoker Michael D. (San Jose CA) Dell\Oca Conrad (Palo Alto CA), Method of die burn-in.
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  74. Lee Sang S. (Sunnyvale CA), Method of forming molded plastic packages with integrated heat sinks.
  75. Ishida Yoshihiro (Tokorozawa JPX) Komatsu Katsuji (Kawagoe JPX) Mimura Seiichi (Kawagoe JPX) Takenouchi Kikuo (Higashimurayama JPX) Yabe Isao (Tokorozawa JPX) Ichikawa Shingo (Sayama JPX) Shimada Yos, Method of making a resin encapsulated pin grid array with integral heatsink.
  76. Juskey Frank J. (Coral Springs FL) Bernardoni Lonnie L. (Coral Springs FL) Freyman Bruce J. (Plantation FL) Suppelsa Anthony B. (Coral Springs FL), Method of making a transfer molded semiconductor device.
  77. Lee Hee G. (Seoul KRX), Method of making integrated circuit package containing inner leads with knurled surfaces.
  78. DiStefano Thomas H. ; Smith John W. ; Mitchell Craig, Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures.
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  93. Michii Kazunari (Itami JPX), Packaged semiconductor device having tab tape and particular power distribution lead structure.
  94. Marrs Robert C. (Scottsdale AZ), Packaged semiconductor die including heat sink with locking feature.
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이 특허를 인용한 특허 (2)

  1. Bridges, Jeremy S.; La Rocca, Paul J.; Megarity, William M., Heat sink for distributing a thermal load.
  2. Zhang, Tonglong, Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the same.
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