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Micropede stacked die component assembly 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
  • H01L-029/40
출원번호 US-0097829 (2005-03-31)
발명자 / 주소
  • Vindasius,Al
  • Robinson,Marc
  • Jacobsen,Larry
  • Almen,Donald
출원인 / 주소
  • Vertical Circuits, Inc.
인용정보 피인용 횟수 : 36  인용 특허 : 76

초록

초록이 없습니다.

대표청구항

대표청구항이 없습니다.

이 특허에 인용된 특허 (76)

  1. Johnson Tony K. (Irvine CA), 3D stack of IC chips having leads reached by vias through passivation covering access plane.
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  2. Bradley Robert F. (New Buffalo MI), Adhesive component means for attaching electrical components to conductors.
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  3. Johnson Randall E. (Carrollton TX) Drumm James M. (Dallas TX), Assembly of semiconductor chips.
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  4. Burns Carmen D. (Austin TX), Bus communication system for stacked high density integrated circuit packages.
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  5. Burns Carmen D. (Austin TX), Bus communication system for stacked high density integrated circuit packages with bifurcated distal lead ends.
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  6. Burns Carmen D. (Austin TX), Bus communication system for stacked high density integrated circuit packages with trifurcated distal lead ends.
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  7. Vindasius Alfons ; Robinson Marc E. ; Scharrenberg William R., Conductive epoxy flip-chip on chip.
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  8. Pedersen David V. (Scotts Valley CA) Finley Michael G. (Cambria CA) Sautter Kenneth M. (Sunnyvale CA), Conductive epoxy flip-chip package and method.
    상세보기
  9. Pedersen David V. ; Finley Michael G. ; Sautter Kenneth M., Conductive epoxy flip-chip package and method.
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  10. Carson John C. (Corona Del Mar CA) Clark Stewart A. (Irvine CA), Detector array module fabrication process.
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  11. Wark James M. (Boise ID), Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
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  12. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
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  13. Poetzinger Steven Eugene, Flexible laminate module including spacers embedded in an adhesive.
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  14. Solomon Allen L. (Fullerton CA), Framed chip hybrid stacked layer assembly.
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  15. Solomon Allen L. (Fullerton CA), Framed chip hybrid stacked layer assembly.
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  16. Berndlmaier Erich (Wappingers Falls NY) Clark Bernard T. (Poughquag NY) Dorler Jack A. (Wappingers Falls NY), Heat transfer structure for integrated circuit package.
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  17. Fassbender Charles J. (Poway CA) Tustaniwskyj Jerry I. (Mission Viejo CA) Vora Harshadrai (Poway CA), High density chip stack having a zigzag-shaped face which accommodates connections between chips.
    상세보기
  18. Gnadinger Alfred P. (Colorado Springs CO), High density data storage using stacked wafers.
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  19. Go Tiong C. (El Toro CA), High density electronic package comprising stacked sub-modules.
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  20. Burns Carmen D. (Austin TX), High density integrated circuit module with snap-on rail assemblies.
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  21. Schmitz Charles E. (Irvine CA) Wimberly Richard C. (Huntington Beach CA) Carlson Donald J. (Tustin CA), High density multi-layered integrated circuit package.
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  22. Go Tiong C. (El Toro CA), High-density electronic modules - process and product.
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  23. Go Tiong C. (El Toro CA), High-density electronic modules－process and product.
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  24. Carson John C. (Corona del Mar CA) Clark Stewart A. (Irvine CA), High-density electronic processing package-structure and fabrication.
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  25. Carson John C. (Corona del Mar CA) Clark Stewart A. (Irvine CA), High-density electronic processing package－structure and fabrication.
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  26. Eide Floyd K. (Huntington Beach CA), IC chip package having chip attached to and wire bonded within an overlying substrate.
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  27. Schmitz Charles E. (Irvine CA), Infrared focal plane module.
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  28. Eide Floyd (Huntington Beach CA), Integrated circuit chip stacking.
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  29. Park Jin-woo (Suwon KRX) Lee Chang-hoon (Seoul KRX), Integrated circuit chip structure.
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  30. Dzarnoski ; Jr. John E. (Poway CA) Babcock James W. (Escondido CA), Layered electronic assembly having compensation for chips of different thickness and different I/O lead offsets.
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  31. Reid Lee R. (Plano TX), Method for fabricating a semiconductor contact and interconnect structure using orientation dependent etching and thermo.
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  32. Vindasius Alfons ; Robinson Marc E. ; Scharrenberg William R., Method for forming conductive epoxy flip-chip on chip.
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  33. Gilton Terry L. (Boise ID), Method for forming custom planar metal bonding pad connectors for semiconductor dice.
    상세보기
  34. Vindasius Alfons ; Sautter Kenneth M., Method for forming vertical interconnect process for silicon segments with dielectric isolation.
    상세보기
  35. Vindasius Alfons ; Sautter Kenneth M., Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform.
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  36. Sliwa ; Jr. John W. (Palo Alto CA), Method of coplanar integration of semiconductor IC devices.
    상세보기
  37. Go ; deceased Tiong C. (late of El Toro CA by Jane C. Go ; executor) Minahan Joseph A. (Simi Valley CA) Shanken Stuart N. (Laguna Niguel CA), Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting.
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  38. Sheppard, Jr., Norman F.; Feakes, Christina M., Methods for conformal coating and sealing microchip reservoir devices.
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  39. Solomon Allen L. (Fullerton CA), Multilayer integrated circuit module.
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  40. Carlson Randolph S. (Carson City NV), Packaging system for stacking integrated circuits.
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  41. Newman, Robert; Johnson, Fred, Process for controlling thickness of die attach adhesive.
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  42. Sugano Toshio (Kokubunji JPX) Nagaoka Kohji (Tobu JPX) Tsukui Seiichiro (Komoro JPX) Wakashima Yoshiaki (Kawasaki JPX) Tanimoto Michio (Kokubunji JPX) Watanabe Masayuki (Yokohama JPX) Sakaguchi Sugur, Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices.
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  43. Kishida Satoru (Itami JPX), Semiconductor integrated circuit device.
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  44. Chance Randal W. (Boise ID) Cloud Eugene H. (Boise ID), Semiconductor package utilizing edge connected semiconductor dice.
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  45. Bertin Claude L. (South Burlington VT) Hedberg Erik L. (Essex Junction VT) Howell Wayne J. (South Burlington VT), Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit.
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  46. Sugano Toshio (Kokubunji) Nagaoka Kohji (Tobu) Tsukui Seiichiro (Komoro) Wakashima Yoshiaki (Kawasaki) Tanimoto Michio (Kokubunji) Watanabe Masayuki (Yokohama) Sakaguchi Suguru (Chigasaki) Nishi Kuni, Semiconductor stacked device.
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  47. Clements Ken (Santa Cruz CA), Semiconductor wafer array.
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  48. Clements Ken (Santa Cruz CA), Semiconductor wafer array with electrically conductive compliant material.
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  49. Pedersen David V. ; Finley Michael G. ; Sautter Kenneth M., Silicon segment programming method.
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  50. Pedersen David V. (Scotts Valley CA) Finley Michael G. (Cambria CA) Sautter Kenneth M. (Sunnyvale CA), Silicon segment programming method and apparatus.
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  51. Walker Kevin E. (Harrisburg PA), Socket for stacking integrated circuit chips.
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  52. Pedersen David V. ; Finley Michael G. ; Sautter Kenneth M., Speaker diaphragm.
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  53. Hatada Kenzo (Katano JPX), Stack type semiconductor package.
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  54. Gates ; Jr. Louis E. (Westlake Village CA) Cochran Richard K. (Ingelwood CA), Stacked chip assembly and manufacturing method therefor.
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  55. Salatino Matthew M. (Satellite Beach FL), Stacked configuration for integrated circuit devices.
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  56. Takiar Hem P. (Fremont CA) Lin Peng-Cheng (Cupertino CA), Stacked multi-chip modules and method of manufacturing.
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  57. Takiar Hem P. (Fremont CA) Lin Peng-Cheng (Cupertino CA), Stacked multi-chip modules and method of manufacturing.
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  58. Takiar Hem P. (Fremont CA) Lin Peng-Cheng (Cupertino CA) Nguyen Luu T. (San Jose CA), Stacked multi-chip modules and method of manufacturing.
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  59. Shokrgozar Hamid (Phoenix AZ) Reeves Leonard (Phoenix AZ) Heggli Bjarne (Phoenix AZ), Stacked silicon die carrier assembly.
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  60. Lin Paul T. (Austin TX) McShane Michael B. (Austin TX), Stacking three dimensional leadless multi-chip module and method for making the same.
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  61. Bertin Claude L. (South Burlington VT) Farrar ; Sr. Paul A. (South Burlington VT) Kalter Howard L. (Colchester VT) Kelley ; Jr. Gordon A. (Essex Junction VT) van der Hoeven Willem B. (Jericho VT) Whi, Three dimensional multichip package methods of fabrication.
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  62. Kato Takashi (Sagamihara JPX) Taguchi Masao (Sagamihara JPX), Three-dimensional integrated circuit and manufacturing method thereof.
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  63. Eichelberger Charles W. (1256 Waverly Pl. Schenectady NY 12308), Three-dimensional multichip module systems.
    상세보기
  64. Bertin Claude L. (South Burlington) Farrar ; Sr. Paul A. (South Burlington) Kalter Howard L. (Colchester) Kelley ; Jr. Gordon A. (Essex Junction) van der Hoeven Willem B. (Jericho) White Francis R. (, Three-dimensional multichip packages and methods of fabrication.
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  65. Robinson William L. (El Toro CA) Roth ; Jr. John C. (Glendora CA), Three-dimensional packaging of focal plane assemblies using ceramic spacers.
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  66. Sato Yoshiyuki (Atsugi JPX) Kiuchi Kazuhide (Atsugi JPX) Watanabe Junji (Tokyo JPX) Koyabu Kunio (Tokyo JPX) Oohata Masanobu (Atsugi JPX) Aoki Katsuhiko (Tokyo JPX), Three-dimensional packaging of semiconductor device chips.
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  67. Tomita Yasuhiro (Neyagawa) Takagi Yoshiyuki (Osaka) Akiyama Shigenobu (Hirakata) Yamazaki Kenichi (Osaka JPX), Three-dimensional stacked LSI.
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  68. Burns Carmen D. (Austin TX) Roane Jerry (Austin TX) Cady James W. (Austin TX), Ultra high density integrated circuit packages.
    상세보기
  69. Burns Carmen D. (Austin TX) Roane Jerry (Austin TX) Cady James W. (Austin TX), Ultra high density integrated circuit packages.
    상세보기
  70. Burns Carmen D. (Austin TX), Ultra high density integrated circuit packages method.
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  71. Burns Carmen D. (Austin TX), Ultra high density integrated circuit packages method and apparatus.
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  72. Burns Carmen D. (Austin TX), Ultra high density modular integrated circuit package.
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  73. Bone Robert (Laguna Niguel CA) Vora Kirti (Irvine CA), Vertical IC chip stack with discrete chip carriers formed from dielectric tape.
    상세보기
  74. Pedersen David V. (Scotts Valley CA) Finley Michael G. (Cambria CA) Sautter Kenneth M. (Sunnyvale CA), Vertical interconnect process for silicon segments.
    상세보기
  75. Vindasius Alfons ; Sautter Kenneth M., Vertical interconnect process for silicon segments with dielectric isolation.
    상세보기
  76. Vindasius Alfons ; Sautter Kenneth M., Vertical interconnect process for silicon segments with thermally conductive epoxy preform.
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이 특허를 인용한 특허 (36)

  1. Robinson, Marc E.; Vindasius, Alfons; Almen, Donald; Jacobsen, Larry, Assembly having stacked die mounted on substrate.
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  2. Vindasius, Al; Robinson, Marc E.; Jacobsen, Larry; Almen, Donald, Assembly having stacked die mounted on substrate.
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  3. Robinson, Marc E.; Vindasius, Alfons; Almen, Donald; Jacobsen, Larry, Die assembly having electrical interconnect.
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  4. Co, Reynaldo; Leal, Jeffrey S.; Pangrle, Suzette K.; McGrath, Scott; Melcher, De Ann Eileen; Barrie, Keith L.; Villavicencio, Grant; Del Rosario, Elmer M.; Bray, John R., Electrical connector between die pad and z-interconnect for stacked die assemblies.
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  5. Co, Reynaldo; Leal, Jeffrey S.; Pangrle, Suzette K.; McGrath, Scott; Melcher, DeAnn Eileen; Barrie, Keith L.; Villavicencio, Grant; del Rosario, Elmer M.; Bray, John R., Electrical connector between die pad and z-interconnect for stacked die assemblies.
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  6. Co, Reynaldo; Villavicencio, Grant; Leal, Jeffrey S.; McElrea, Simon J. S., Electrical interconnect for die stacked in zig-zag configuration.
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  7. McElrea, Simon J. S.; Andrews, Jr., Lawrence Douglas; McGrath, Scott; Caskey, Terrence; Crane, Scott Jay; Robinson, Marc E.; Cantillep, Loreto, Electrically interconnected stacked die assemblies.
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  8. McElrea, Simon J. S.; Andrews, Jr., Lawrence Douglas; McGrath, Scott; Caskey, Terrence; Crane, Scott Jay; Robinson, Marc E.; Cantillep, Loreto, Electrically interconnected stacked die assemblies.
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  9. Tao, Min; Sun, Zhuowen; Kim, Hoki; Zohni, Wael; Agrawal, Akash, Enhanced density assembly having microelectronic packages mounted at substantial angle to board.
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  10. von Kaenel, Vincent R., Flexible packaging for chip-on-chip and package-on-package technologies.
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  11. Katkar, Rajesh; Co, Reynaldo; McGrath, Scott; Prabhu, Ashok S.; Lee, Sangil; Wang, Liang; Shen, Hong, Flipped die stack.
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  12. Prabhu, Ashok S.; Katkar, Rajesh; Wang, Liang; Uzoh, Cyprian Emeka, Flipped die stack assemblies with leadframe interconnects.
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  13. Delacruz, Javier A.; Haba, Belgacem; Vu, Tu Tam; Katkar, Rajesh, Flipped die stacks with multiple rows of leadframe interconnects.
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  14. Delacruz, Javier A.; Haba, Belgacem; Vu, Tu Tam; Katkar, Rajesh, Flipped die stacks with multiple rows of leadframe interconnects.
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  15. Jones, Rodyn; Vancouvering, Ken, Location sensitive solid state drive.
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  16. Jones, Roydn; Vancouvering, Ken, Location sensitive solid state drive.
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  17. Jones, Roydn; Vancouvering, Ken, Location sensitive solid state drive.
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  18. Haba, Belgacem; Sun, Zhuowen; Delacruz, Javier A., Microelectronic packages and assemblies with improved flyby signaling operation.
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  19. Pyeon, Hong Beom, Package-level integrated circuit connection without top metal pads or bonding wire.
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  20. Jones, Roydn, Radiation-shielded semiconductor assembly.
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  21. Leal, Jeffrey S., Selective die electrical insulation by additive process.
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  22. Leal, Jeffrey S., Selective die electrical insulation by additive process.
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  23. Jang, Chul-yong; Jang, Ae-nee; Kim, Young-lyong, Semiconductor chip connecting semiconductor package.
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  24. Co, Reynaldo; Melcher, DeAnn Eileen; Pan, Weiping; Villavicencio, Grant, Semiconductor die array structure.
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  25. Barrie, Keith Lake; Pangrie, Suzette K.; Villavicencio, Grant; Leal, Jeffrey S., Semiconductor die having fine pitch electrical interconnects.
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  26. Crane, Scott Jay; McElrea, Simon J. S.; McGrath, Scott; Pan, Weiping; Melcher, De Ann Eileen; Robinson, Marc E., Semiconductor die mount by conformal die coating.
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  27. Crane, Scott Jay; McElrea, Simon J. S.; McGrath, Scott; Pan, Weiping; Melcher, De Ann Eileen; Robinson, Marc E., Semiconductor die mount by conformal die coating.
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  28. Crane, Scott Jay; McElrea, Simon J. S.; McGrath, Scott; Pan, Weiping; Melcher, DeAnn Eileen; Robinson, Marc E., Semiconductor die mount by conformal die coating.
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  29. Kim, Kilsoo; Kang, SunWon, Semiconductor package.
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  30. Kim, Kilsoo; Kang, SunWon, Semiconductor package.
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  31. McGrath, Scott; Leal, Jeffrey S.; Shenoy, Ravi; Cantillep, Loreto; McElrea, Simon; Pangrle, Suzette K., Stacked die assembly having reduced stress electrical interconnects.
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  32. McElrea, Simon J. S.; Robinson, Marc E.; Andrews, Jr., Lawrence Douglas, Support mounted electrically interconnected die assembly.
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  33. McElrea, Simon J. S.; Robinson, Marc E.; Andrews, Jr., Lawrence Douglas, Support mounted electrically interconnected die assembly.
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  34. Vindasius, Al; Robinson, Marc, Three dimensional six surface conformal die coating.
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  35. Prabhu, Ashok S.; Katkar, Rajesh; Moran, Sean, Wafer-level flipped die stacks with leadframes or metal foil interconnects.
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  36. Prabhu, Ashok S.; Katkar, Rajesh; Moran, Sean, Wafer-level flipped die stacks with leadframes or metal foil interconnects.
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