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Input pipeline registers for a node in an adaptive computing engine 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/38
  • G06F-013/00
출원번호 US-0626479 (2003-07-23)
발명자 / 주소
  • Ramchandran,Amit
출원인 / 주소
  • NVIDIA Corporation
대리인 / 주소
    Patterson & Sheridan, LLP
인용정보 피인용 횟수 : 62  인용 특허 : 21

초록

초록이 없습니다.

대표청구항

대표청구항이 없습니다.

이 특허에 인용된 특허 (21)

  1. Worley ; Jr. William S. (Saratoga CA) Bryg William R. (Saratoga CA) Baum Allen (Palo Alto CA), Cache memory consistency control with explicit software instructions.
    상세보기
  2. Baldwin David R. (Weybridge GBX), Computer system with clock shared between processors executing separate instruction streams.
    상세보기
  3. Abbott, Curtis; Shahri, Homayoun, Count/address generation circuitry.
    상세보기
  4. Hoogerbrugge, Jan; Augusteijn, Alexander, Data processing device, method of executing a program and method of compiling.
    상세보기
  5. Santhanam Vatsa (Campbell CA), Efficient explicit data prefetching analysis and code generation in a low-level optimizer for inserting prefetch instruc.
    상세보기
  6. Roth, Charles P.; Singh, Ravi P.; Overkamp, Gregory A., Exception handling using an exception pipeline in a pipelined processor.
    상세보기
  7. Suzuki Kazumasa (Tokyo JPX), Hardware arrangement of effectively expanding data processing time in pipelining in a microcomputer system and a method.
    상세보기
  8. Nukiyama Tomoji (Tokyo JPX), Interface circuit having a shift register inserted between a data transmission unit and a data reception unit.
    상세보기
  9. Horst Robert W., Logical, fail-functional, dual central processor units formed from three processor units.
    상세보기
  10. Greenfield, Zvi, Method and apparatus for communicating between multiple functional units in a computer environment.
    상세보기
  11. Fraser, Christopher Warwick, Method and system for compressing program code and interpreting compressed program code.
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  12. Budrovic, Martin T.; Kolson, David J., Methods, systems, and computer program products for compressing a computer program based on a compression criterion and executing the compressed program.
    상세보기
  13. Witt David B., Microprocessor with dynamically extendable pipeline stages and a classifying circuit.
    상세보기
  14. Araki Toshiyuki,JPX ; Aoki Katsuji,JPX, Motion vector detection apparatus.
    상세보기
  15. Takeda Masaki,JPX, Pipeline processing device, clipping processing device, three-dimensional simulator device and pipeline processing metho.
    상세보기
  16. Bartkowiak John G. ; Lynch Thomas W., Processor having a bus interconnect which is dynamically reconfigurable in response to an instruction field.
    상세보기
  17. Donohoe, Gregory, Reconfigurable data path processor.
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  18. Chiang John M., Register access controller which prevents simultaneous coupling of more than one register to a bus interface.
    상세보기
  19. Edwards Stephen W. (Madison AL), Self-clocking pipeline register.
    상세보기
  20. Yamanaka, Hidekazu; Horiyama, Takashi, Self-synchronous logic circuit having test function and method of testing self-synchronous logic circuit.
    상세보기
  21. De Oliveira Kastrup Pereira, Bernardo; Bink, Adrianus J.; Hoogerbrugge, Jan, System for executing computer program using a configurable functional unit, included in a processor, for executing configurable instructions having an effect that are redefined at run-time.
    상세보기

이 특허를 인용한 특허 (62)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
    상세보기
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
    상세보기
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
    상세보기
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
    상세보기
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
    상세보기
  10. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
    상세보기
  11. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
    상세보기
  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
    상세보기
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
    상세보기
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
    상세보기
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
    상세보기
  16. Ching, Alvin Y.; Wong, Jennifer; New, Bernard J.; Simkins, James M.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Architectural floorplan for a digital signal processing circuit.
    상세보기
  17. Wong, Anna Wing Wah; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Simkins, James M.; Vadi, Vasisht Mantra; Schultz, David P., Arithmetic logic unit circuit.
    상세보기
  18. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
    상세보기
  19. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
    상세보기
  20. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
    상세보기
  21. Alexander, Praveen; Liao, Heng, DMA address translation scheme and cache with modified scatter gather element including SG list and descriptor tables.
    상세보기
  22. New, Bernard J.; Vadi, Vasisht Mantra; Wong, Jennifer; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M., Digital signal processing block having a wide multiplexer.
    상세보기
  23. Simkins, James M.; Ching, Alvin Y.; Thendean, John M.; Vadi, Vasisht M.; Poon, Chi Fung; Rab, Muhammad Asim, Digital signal processing block with preadder stage.
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  24. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having a SIMD circuit.
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  25. Vadi, Vasisht Mantra; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M., Digital signal processing circuit having a pattern circuit for determining termination conditions.
    상세보기
  26. Vadi, Vasisht Mantra; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M., Digital signal processing circuit having a pattern detector circuit.
    상세보기
  27. New, Bernard J.; Wong, Jennifer; Simkins, James M.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having a pattern detector circuit for convergent rounding.
    상세보기
  28. Simkins, James M.; Thendean, John M.; Vadi, Vasisht Mantra; New, Bernard J.; Wong, Jennifer; Wong, Anna Wing Wah; Ching, Alvin Y., Digital signal processing circuit having a pre-adder circuit.
    상세보기
  29. Thendean, John M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Simkins, James M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having an adder circuit with carry-outs.
    상세보기
  30. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having input register blocks.
    상세보기
  31. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra; Schultz, David P., Digital signal processing element having an arithmetic logic unit.
    상세보기
  32. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
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  33. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
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  34. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
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  35. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
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  36. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
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  37. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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  38. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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  39. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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  40. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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  41. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
    상세보기
  42. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
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  43. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
    상세보기
  44. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
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  45. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
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  46. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
    상세보기
  47. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
    상세보기
  48. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
    상세보기
  49. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
    상세보기
  50. Scheuermann, W. James, Method and system for reconfigurable channel coding.
    상세보기
  51. Scheuermann, W. James, Method and system for reconfigurable channel coding.
    상세보기
  52. Scheuermann, W. James, Method and system for reconfigurable channel coding.
    상세보기
  53. Scheuermann, W. James, Method and system for reconfigurable channel coding.
    상세보기
  54. Wendling, Xavier; Simkins, James M., Method of and circuit for implementing a filter in an integrated circuit.
    상세보기
  55. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
    상세보기
  56. Asano, Shigehiro; Yoshikawa, Takashi, Pipeline processing communicating adjacent stages and controls to prevent the address information from being overwritten.
    상세보기
  57. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
    상세보기
  58. Master,Paul L.; Watson,John, Storage and delivery of device features.
    상세보기
  59. Alexander, Praveen; Yi, Cheng; Zhong, Tao; Clinton, David J.; Nichols, Gary, System and method for scatter gather cache processing.
    상세보기
  60. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
    상세보기
  61. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
    상세보기
  62. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
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