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Method and apparatus for forming an underfill adhesive layer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/02
출원번호 US-0224291 (2002-08-19)
등록번호 US-7253078 (2007-08-07)
발명자 / 주소
  • Nguyen,Luu T.
  • Nguyen,Hau T.
  • Patwardhan,Viraj A.
  • Kelkar,Nikhil
  • Mostafazadeh,Shahram
출원인 / 주소
  • National Semiconductor Corporation
대리인 / 주소
    Beyer Weaver LLP
인용정보 피인용 횟수 : 12  인용 특허 : 58

초록

An apparatus and method for forming a layer of underfill adhesive on an integrated circuit in wafer form is described. In one embodiment, the layer of underfill adhesive is disposed and partially cured on the active surface of the wafer. Once the underfill adhesive has partially cured, the wafer is

대표청구항

The invention claimed is: 1. A method, comprising: fabricating a plurality of integrated circuit dice on an active surface of a wafer; fabricating one or more electrically conductive pads on each of the dice on the active surface of the wafer respectively; forming solder bumps on the one or more el

이 특허에 인용된 특허 (58)

  1. Pennisi Robert W. (Boca Raton FL) Papageorge Marc V. (Plantation FL), Adhesive and encapsulant material with fluxing properties.
  2. Pennisi Robert W. (Boca Raton FL) Papageorge Marc V. (Plantation FL) Urbish Glenn F. (Coral Springs FL), Anisotropic conductive adhesive and encapsulant material.
  3. Ference Thomas G. (Carmel NY) Gruber Peter A. (Mohegan Lake NY) Hernandez Bernardo (Norwalk CT) Palmer Michael J. (Walden NY) Zingher Arthur R. (White Plains NY), Apparatus and method for injection molding solder and applications thereof.
  4. Boyko Christina M. ; Ingraham Anthony P. ; Markovich Voya R. ; Russell David J., Ball limiting metal mask and tin enrichment of high melting point solder for low temperature interconnection.
  5. Andricacos Panayotis Constantinou ; Datta Madhav ; Horkans Wilma Jean ; Kang Sung Kwon ; Kwietniak Keith Thomas, Barrier layers for electroplated SnPb eutectic solder joints.
  6. Kaneyuki Kato JP, Circuit device with bonding strength improved and method of manufacturing the same.
  7. Nagai, Akira; Eguchi, Shuji; Ogino, Masahiko; Segawa, Masanori; Ishii, Toshiak; Tsuyuno, Nobutake; Kokaku, Hiroyoshi; Hattori, Rie; Morishima, Makoto; Anjoh, Ichiro; Tsubosaki, Kunihiro; Miyazaki, Ch, Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same.
  8. Scholz Kenneth D. (4150 Willmar Dr. Palo Alto CA 94306), Compressive bump-and-socket interconnection scheme for integrated circuits.
  9. Fogal Rich ; Wood Alan G., Condensed memory matrix.
  10. Bryant Frank Randolph (Denton TX) Singh Abha Rani (Carrollton TX), Double mask hermetic passivation structure.
  11. Capote Miguel A. (4151 Parkside Pl. Carlsbad CA 92008 4) Todd Michael G. (748 Galaxy Vista CA 92084) Manesis Nicholas J. (416 Coyote Creek Cir. San Jose CA 95116) Craig Hugh P. (3400 Hill St. ; No. 1, Electrically conductive compositions and methods for the preparation and use thereof.
  12. Milkovich Cynthia S. ; Pierson Mark V. ; Tran Son K., Encapsulation of solder bumps and solder connections.
  13. Oroskar Anil R. (Downers Grove IL) Johnson James L. (Des Plaines IL), Enhanced membrane separation of monosaccharides utilizing concentration polarization.
  14. DeFelice Richard Alden ; Dittmann Eric William ; Sullivan Paul A., Flip chip assembly of semiconductor IC chips.
  15. Beddingfield Stanley Craig, Flip chip bump structure and method of making.
  16. Gilleo Kenneth Burton ; Blumel David, Flip chip with integrated mask and underfill.
  17. Shih-Kuang Chiu TW; Ying-Chou Tsai TW, Flip-chip semiconductor package structure and process for fabricating the same.
  18. Kazuaki Sumita JP; Kimitaka Kumagae JP; Miyuki Wakao JP; Toshio Shiobara JP, Flip-chip type semiconductor device sealing material and flip-chip type semiconductor device.
  19. Thomas McCarthy ; Michael Wagaman ; David Schwind, Highly stable packaging substrates.
  20. Robinson Douglas S. (Ames IA) Jensen Terrence C. (Ames IA) Gray Joseph N. (Ames IA), Integrated energy-sensitive and position-sensitive x-ray detection system.
  21. Mitchell Douglas G. ; Carney Francis J. ; Woolsey Eric J., Interconnect system and method of fabrication.
  22. Mostafazadeh Shahram ; Smith Joseph O., Lead frame chip scale package.
  23. Kelkar Nikhil Vishwanath ; Kao Pai-Hsiang, Metal pads for electrical probe testing on wafer with bump interconnects.
  24. Luu Nguyen ; Nikhil Kelkar ; Christopher Quentin ; Ashok Prabhu ; Hem P. Takiar, Method and apparatus for forming an underfill adhesive layer.
  25. Chen Yu ; Gerber Joel A. ; Schreiber Brian E. ; Smith Joshua W., Method for making circuit elements for a z-axis interconnect.
  26. Saitoh Masaru,JPX, Method for manufacturing a flip chip semiconductor device.
  27. Yoshifumi Nakamura JP; Yoshihiro Bessho JP; Minehiro Itagaki JP, Method for manufacturing electronic device with resin layer between chip carrier and circuit wiring board.
  28. Shibata, Kazutaka, Method of cutting a wafer into individual chips.
  29. Lin Jong-Kai (Chandler AZ) Lytle William H. (Chandler AZ) Subrahmanyan Ravichandran (Mesa AZ), Method of forming an electrical interconnect.
  30. Akram Salman, Method of forming conductive bumps on die for flip chip applications.
  31. Wang Hsueh-Te,TWX ; Tao Su,TWX, Method of making stacked chip package.
  32. Pasadyn, Alexander J.; Bode, Christopher A., Method of using damaged areas of a wafer for process qualifications and experiments, and system for accomplishing same.
  33. Shahram Mostafazadeh, Method to encapsulate bumped integrated circuit to create chip scale package.
  34. Holzapfel Paul ; Schlueter James ; Karlsrud Chris ; Lin Warren, Methods and apparatus for detecting removal of thin film layers during planarization.
  35. Morrell Michelle J. ; Machuga Steven C.,DEX ; O'Malley Grace M. ; Carson George A. ; Skipor Andrew ; Zhou Wen Xu ; Wyatt Karl W., Microelectronic assembly including polymeric reinforcement on an integrated circuit die, and method for forming same.
  36. Schueller, Randolph D., Multi-metal layer circuit.
  37. Eichelberger Charles W. (Schenectady NY), Multichip integrated circuit modules.
  38. Mashimoto Yohko,JPX ; Inoue Shuji,JPX ; Kubota Jiro,JPX ; Kuroda Mashahiro,JPX, Multiregion solder interconnection structure.
  39. Joseph A. Benenati ; Claude L. Bertin ; William T. Chen ; Thomas E. Dinan ; Wayne F. Ellis ; Wayne J. Howell ; John U. Knickerbocker ; Mark V. Pierson ; William R. Tonti ; Jerzy M. Zalesinsk, Rolling ball connector.
  40. Abe Mitsuo,JPX ; Kubota Yoshihiro,JPX ; Katoh Yoshitsugu,JPX ; Hayakawa Michio,JPX ; Nomoto Ryuji,JPX ; Sato Mitsutaka,JPX ; Orimo Seiichi,JPX ; Inoue Hiroshi,JPX ; Hamano Toshio,JPX, Semiconductor device and method of producing the same.
  41. Yamaji Yasuhiro,JPX, Semiconductor device for a face down bonding to a mounting substrate and a method of manufacturing the same.
  42. Yamaji Yasuhiro,JPX, Semiconductor device for face down bonding to a mounting substrate and a method of manufacturing the same.
  43. Norio Fukasawa JP; Hirohisa Matsuki JP; Kenichi Nagashige JP; Yuzo Hamanaka JP; Muneharu Morioka JP, Semiconductor device having a ball grid array and a fabrication process thereof.
  44. Akiyama Yukiharu,JPX ; Kudaishi Tomoaki,JPX ; Ohnishi Takehiro,JPX ; Shimada Noriou,JPX ; Eguchi Shuji,JPX ; Nishimura Asao,JPX ; Anjo Ichiro,JPX ; Tsubosaki Kunihiro,JPX ; Miyazaki Chuichi,JPX ; Koy, Semiconductor device with chip size package.
  45. Haji, Hiroshi; Sakemi, Shoji, Semiconductor device with reinforcing resin layer.
  46. Capote Miguel A. ; Zhu Xiaoqi, Semiconductor flip-chip assembly with pre-applied encapsulating layers.
  47. Capote Miguel A. ; Zhou Zhiming ; Zhu Xiaoqi ; Zhou Ligui, Semiconductor flip-chip package and method for the fabrication thereof.
  48. Benjamin N. Eldridge, Semiconductor fuse covering.
  49. Akamatsu Hiroshi,JPX, Semiconductor integrated circuit device incorporating fuse-programmable pass/fail identification circuit and pass/fail d.
  50. Morihara Toshinori (Hyogo JPX), Semiconductor memory device having SOI structure and manufacturing method thereof.
  51. Kao Pai-Hsiang ; Schaefer William Jeffrey ; Kelkar Nikhil Vishwanath, Semiconductor wafer having a bottom surface protective coating.
  52. Mis Joseph Daniel ; Adema Gretchen Maerker ; Kellam Mark D. ; Rogers W. Boyd, Solder bump fabrication methods and structure including a titanium barrier layer.
  53. Christie Frederick Richard (Endicott NY) Papathomas Kostas I. (Endicott NY) Wang David Wei (Vestal NY), Solder interconnection structure and process for making.
  54. Nishiguchi Masanori (Yokohama JPX) Miki Atsushi (Yokohama JPX), Substrate for packaging a semiconductor device.
  55. Nguyen Luu ; Takiar Hem P. ; Warner Ethan ; Mostafazadeh Shahram ; Smith Joseph O., Techniques for wafer level molding of underfill encapsulant.
  56. Iida Kazutoshi,JPX ; Wigham Jon,IEX, Thermosetting resin compositions.
  57. Qi, Jing; Danvir, Janice; Klosowiak, Tomasz, Wafer coating and singulation method.
  58. Tao, Su; Yee, Kuo-Chung; Kao, Jen-Chieh; Chen, Chih-Lung; Liau, Hsing-Jung, Wafer-level package with a cavity and fabricating method thereof.

이 특허를 인용한 특허 (12)

  1. Jiang,Tongbi; Luo,Shijian, Electronic devices at the wafer level having front side and edge protection material and systems including the devices.
  2. Chow, Seng Guan; Huang, Rui; Kuan, Heap Hoe, Integrated circuit package system with wire-in-film encapsulation.
  3. Chow, Seng Guan; Shim, Il Kwon; Kuan, Heap Hoe; Kim, Youngcheol, Integrated circuit packaging system with reinforced encapsulant having embedded interconnect and method of manufacture thereof.
  4. Lee, Michael G., Method and system for providing a reliable semiconductor assembly.
  5. Dotsenko, Vladimir V., Method for fabrication of electrical contacts to superconducting circuits.
  6. Jiang, Tongbi; Luo, Shijian, Methods for applying front side and edge protection material to electronic devices at the wafer level, devices made by the methods, and systems including the devices.
  7. Ferger, Claudius; Gaynes, Michael A.; Nah, Jae-Woong; Shih, Da-Yuan, No flow underfill or wafer level underfill and solder columns.
  8. Fukuta, Kazuhiko; Toyosawa, Kenji, Sealed-by-resin type semiconductor device.
  9. Serrano, Esteban Arturo Alvarez; Sánchez, Horman Armando Millán, Selective soldering bath.
  10. Serrano, Esteban Arturo Alvarez; Fonseca, Julian Martinez; Sánchez, Hozman Armando Millán, Selective soldering system.
  11. Dotsenko, Vladimir V., Superconductive multi-chip module for high speed digital circuits.
  12. Wu, Cheng-Tar; Liu, Chung-Shi; Lin, Chih-Wei; Huang, Hui-Min; Lin, Chun-Cheng; Cheng, Ming-Da, Wafer level chip scale package interconnects and methods of manufacture thereof.
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