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A method and apparatus for aggregating power from multiple sources generates a single direct current regulated voltage. The apparatus comprises a plurality of slave voltage converters and a master pulse width modulator circuit. Providing a plurality of direct current power sources, current is drawn

A method and apparatus for aggregating power from multiple sources generates a single direct current regulated voltage. The apparatus comprises a plurality of slave voltage converters and a master pulse width modulator circuit. Providing a plurality of direct current power sources, current is drawn through a plurality of lines connected to the plurality of direct current power sources. An open circuit voltage for each direct current power source is unknown. Each line of the plurality of lines has a line resistance. The line resistance of at least some of the plurality of lines may be unknown. The line resistance of at least some of the plurality of lines is large. The single direct current regulated voltage is generated from the drawn current.

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What is claimed is: 1. A method for aggregating power from multiple sources comprising: (a) providing a plurality of direct current power sources; (b) drawing current through a plurality of lines connected to the plurality of direct current power sources, wherein the current drawn in each of said p

What is claimed is: 1. A method for aggregating power from multiple sources comprising: (a) providing a plurality of direct current power sources; (b) drawing current through a plurality of lines connected to the plurality of direct current power sources, wherein the current drawn in each of said plurality of lines is performed by switching the current in response to a modified pulse width modulated (PWM) signal, wherein each modified PWM signal is a modified form of a master PWM signal, the modified PWM signal being generated by limiting a pulse width of the master PWM signal such that a closed circuit voltage corresponding to a voltage across the line while drawing the current is at least one half of an open circuit voltage corresponding to a voltage across the direct current power source from which the current is drawn; and (c) generating a single direct current regulated voltage from the current drawn in (b). 2. The invention of claim 1 wherein the maximum open circuit voltage is 200 volts. 3. The invention of claim 1 wherein the power drawn from each direct current power source of the plurality of direct current power sources is up to 15 watts. 4. The invention of claim 1 wherein the power drawn from each direct current power source of the plurality of direct current power sources is up to 12.5 watts. 5. The invention of claim 1 wherein the single direct current regulated voltage is 12 volts. 6. The invention of claim 1 wherein at least some of the lines have a total line resistance of at least 1 kohms. 7. The invention of claim 1 wherein the plurality of lines comprise xDSL lines. 8. The invention of claim 7 wherein the xDSL lines are HDSL2 lines. 9. The invention of claim 7 wherein the xDSL lines are HDSL4 lines. 10. The invention of claim 1, wherein the switching performed in response to the modified pulse width modulated signal comprises, for each line, limiting a pulse width of the master pulse width modulated signal such that the power drawn from each direct current power source of the plurality of direct current power sources is up to 15 watts. 11. The invention of claim 1, wherein the switching performed in response to the modified pulse width modulated signal comprises, for each line, limiting a pulse width of the master pulse width modulated signal such that the power drawn from each direct current power source of the plurality of direct current power sources is up to 12.5 watts. 12. The invention of claim 1, wherein said switching comprises forming a master pulse width modulated signal, wherein said forming comprises adjusting a duty cycle of the master pulse width modulated signal according to the single direct current regulated voltage. 13. The invention of claim 1 further comprising rectifying and filtering the current drawn in (b) that is switched. 14. An apparatus for aggregating power from multiple sources comprising circuitry that implements the method of claim 1. 15. An apparatus for aggregating power from multiple sources, the apparatus connected to a plurality of direct current power sources by a plurality of lines, wherein each direct current power source of the plurality of direct current power sources has an open circuit voltage, wherein the open circuit voltage is unknown, wherein a maximum value of the open circuit voltage is known, wherein each line of the plurality of lines has a line resistance, the apparatus comprising: power aggregation circuitry connected to the plurality of lines; wherein said power aggregation circuitry draws current through the plurality of lines from the plurality of direct current power sources; wherein said power aggregation circuitry limits the current drawn through the plurality of lines such that, for each line of the plurality of lines, a closed circuit voltage corresponding to a voltage across the line while drawing current is at least one half of the maximum open circuit voltage; wherein said power aggregation circuitry generates a single direct current regulated voltage from the drawn current; and wherein said power aggregation circuitry comprises a master pulse width modulator circuit for producing a master pulse width modulator signal, wherein the current drawn in each of said plurality of lines is performed by switching the current in response to a modified pulse width modulated (PWM) signal, wherein each modified PWM signal is a modified form of a master PWM signal, the modified PWM signal being generated by limiting a pulse width of the master pulse width modulated signal such that a closed circuit voltage corresponding to a voltage across the line while drawing the current is at least one half of an open circuit voltage corresponding to a voltage across the direct current power source from which the current is drawn. 16. The invention of claim 15 wherein said power aggregation circuitry comprises: a master pulse width modulator circuit for producing a master pulse width modulator signal; and a plurality of slave voltage converters wherein each slave voltage converter of said plurality of slave voltage converters is connected to a line of the plurality of lines, wherein each slave voltage converter receives said master pulse width modulator signal, wherein each slave voltage converter is operative to modify said master pulse width modulator signal according to a voltage comparison and a current measurement, wherein said master pulse width modulator signal is used to switch the drawn current from the line through a power stage of said slave voltage converter. 17. The invention of claim 16 wherein a duty cycle of said master pulse width modulator signal varies according to the single direct current regulated voltage. 18. The invention of claim 16 wherein said power stage comprises one of the following converters: a forward converter, a flyback converter, a cuk converter, a single-ended-primary-inductance converter, a center-tapped push-pull converter, a full-bridge converter, a half-bridge converter. 19. The invention of claim 16 wherein each slave voltage converter of said plurality of slave voltage converters is operative to modify said master pulse width modulator signal such that the power drawn from each direct current power source of the plurality of direct current power sources is up to around 15 watts. 20. The invention of claim 16 wherein each slave voltage converter of said plurality of slave voltage converters is operative to modify said master pulse width modulator signal such that the power drawn from each direct current power source of the plurality of direct current power sources is up to around 12.5 watts. 21. The invention of claim 16 wherein each slave voltage converter of said plurality of slave voltage converters comprises startup circuitry for initiating a startup operation of said slave voltage converter. 22. The invention of claim 15 wherein said single direct current regulated voltage is 12 volts. 23. An apparatus for aggregating power from multiple sources and generating a single direct current regulated voltage, the apparatus connected to a plurality of direct current power sources by a plurality of lines, wherein each direct current power source of the plurality of direct current power sources has an open circuit voltage, wherein the open circuit voltage is unknown, wherein a maximum value of the open circuit voltage is known, wherein each line of the plurality of lines has a line resistance, wherein the line resistance of at least some of the plurality of lines is large, the apparatus comprising: a plurality of slave voltage converters wherein each slave voltage converter of said plurality of slave voltage converters comprises an input voltage port, an output voltage port, and a sync input, wherein said input voltage port of each slave voltage converter is connected to a line of the plurality of lines, wherein all output voltage ports of said plurality of slave voltage converters are conjoined; and a master pulse width modulator circuit comprising a master pulse width modulator circuit input and a master pulse width modulator circuit output, said master pulse width modulator circuit input connected to said output voltage port that is conjoined, said master pulse width modulator circuit output connected to said sync input of each slave voltage converter of said plurality of slave voltage converters. 24. The invention of claim 23 wherein said master pulse width modulator circuit further comprises an external sync input. 25. The invention of claim 23 wherein said master pulse width modulator circuit comprises: a master pulse width modulator comprising an input and an output; an error amplifier circuit connected to said output voltage port that is conjoined and to said input of said master pulse width modulator; a capacitor connected to said output of said master pulse width modulator; and an isolation device connected to said capacitor, and to said master pulse width modulator circuit output. 26. The invention of claim 23 wherein each slave voltage converter of said plurality of slave voltage converters comprises: an input rectifier connected to said input voltage port; a filter connected to said input rectifier for producing a filtered input voltage; a v-servo circuit for comparing the filtered input voltage to a reference voltage; an i-servo circuit including a resistor for sensing a current threshold on said input voltage port; a pulse width limiter connected to said v-servo circuit and said i-servo circuit for producing a pulse width limiter output signal; a sync circuit connected to said pulse width limiter, and to said master pulse width modulator circuit output; a startup circuit connected to said sync circuit; a startup resistor connected to said filter; a startup capacitor connected to said startup resistor; and a power stage connected to said pulse width limiter; wherein said startup circuit receives a startup signal from said startup resistor and said startup capacitor, wherein said startup signal causes said startup circuit, said sync circuit, and said pulse width limiter to produce an oscillator signal, wherein said oscillator signal is received by said power stage, wherein said power stage produces an output voltage, wherein said output voltage causes said master pulse width modulator circuit to output a master pulse width modulator signal, wherein said master pulse width modulator signal is received by said sync circuit; wherein said sync circuit provides said master pulse width modulator signal to said pulse width limiter; wherein said pulse width limiter limits a pulse width of said master pulse width modulator signal according to a signal provided by said v-servo circuit and said i-servo circuit; and wherein said power stage produces an output voltage on said output voltage port by switching and filtering said filtered input voltage according to said pulse width limiter output signal. 27. The invention of claim 26 wherein said power stage is a power stage selected from the group of power stages consisting of a forward converter, a flyback converter, a cuk converter, a single-ended-primary-inductance converter, a center-tapped push-pull converter, a full-bridge converter, and a half-bridge converter. 28. The invention of claim 26 wherein said pulse width limiter, said sync circuit, and said startup circuit is a single integrated device. 29. The invention of claim 23 wherein said master pulse width modulator circuit further comprises an external sync input. 30. An apparatus for aggregating power from multiple sources and generating a single direct current regulated voltage, the apparatus connected to a plurality of direct current power sources by a plurality of lines, wherein each direct current power source of the plurality of direct current power sources has an open circuit voltage, wherein the open circuit voltage is unknown, wherein a maximum value of the open circuit voltage is known, wherein each line of the plurality of lines has a line resistance, wherein the line resistance of at least some of the plurality of lines is large, the apparatus comprising: a plurality of slave voltage converters wherein each slave voltage converter of said plurality of slave voltage converters comprises: rectifier means connected to a line of the plurality of lines for rectifying the open circuit voltage; filter means connected to the rectifier means for producing a filtered voltage; startup means for producing a startup signal from said filtered voltage; pulse width modulator means for producing a pulse width modulator output; sync means connected to said pulse width modulator means for causing said pulse width modulator means to initiate a startup cycle according to said startup signal, and for supplying a master pulse width modulated output signal to said pulse width modulator means after said startup cycle; power stage means for producing a direct current voltage according to said pulse width modulator output by switching said filtered voltage; i-servo means for causing said pulse width modulator means to modify said pulse width modulator output; v-servo means for causing said pulse width modulator means to modify said pulse width modulator output; and linear regulator means for providing power to said i-servo means and said v-servo means; a master pulse width modulator circuit connected to said plurality of slave voltage converters, said master pulse width modulator circuit comprising: error amplifier means for producing an error signal proportional to the single direct current regulated voltage; master pulse width modulator means for receiving said error signal and producing said master pulse width modulated output signal; and isolation means for isolating said master pulse width modulated output signal.