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Method for manufacturing and testing semiconductor devices on a resin-coated wafer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-031/02
출원번호 US-0279988 (2002-10-25)
등록번호 US-7262610 (2007-08-28)
우선권정보 JP-11-66621(1999-03-12)
발명자 / 주소
  • Ohtaki,Mikio
출원인 / 주소
  • Oki Electric Industry Co., Ltd.
대리인 / 주소
    Rabin & Berdo, P.C.
인용정보 피인용 횟수 : 3  인용 특허 : 33

초록

A semiconductor device test apparatus according to the present invention includes a circuit board 103 and a film 105. A plurality of electrodes 103c are formed at the circuit board 103 at positions that face opposite a plurality of electrodes 201a at a device to be measured 201, whereas bumps 105b a

대표청구항

What is claimed is: 1. A method for manufacturing semiconductor devices, the method comprising: providing a semiconductor wafer with a wafer surface having a plurality of circuit elements formed thereon; forming on the wafer surface a plurality of electrodes connected with the circuit elements; coa

이 특허에 인용된 특허 (33)

  1. Tsujide Tohru (Tokyo JPX) Hishii Toshiyasu (Tokyo JPX) Nakaizumi Kazuo (Tokyo JPX), Apparatus for testing semicondctor wafer.
  2. Lin Paul T. (Austin TX), Composite flip chip semiconductor device with an interposer having test contacts formed along its periphery.
  3. Khoury Theodore A. ; Frame James W., Contact structure and production method thereof.
  4. Dranchak David William ; Kelleher Robert Joseph ; Pagnani David Peter ; Zippetelli Patrick Robert, Dual substrate package assembly coupled to a conducting member.
  5. Suyama Shinichi (Iruma JPX) Haruta Yuiti (Hirakata JPX), Electric inspection unit using anisotropically electroconductive sheet.
  6. Ban, Naoto; Namba, Masaaki; Hasebe, Akio; Wada, Yuji; Kohno, Ryuji; Seito, Akira; Motoyama, Yasuhiro, Fabrication method of semiconductor integrated circuit device and its testing apparatus.
  7. Devereaux Kevin M. (Boise ID) Bunn Mark (Boise ID) Higgins Brian (Boise ID), Fixture for burn-in testing of semiconductor wafers.
  8. Yamaji Yasuhiro,JPX ; Hosomi Eiichi,JPX, Manufacturing method of semiconductor device.
  9. Crumly William R. (Anaheim CA), Membrane connector with stretch induced micro scrub.
  10. John L. Pierce, Method for constructing a wafer interposer by using conductive columns.
  11. Gross David E. (Dripping Springs TX), Method for manufacturing a semiconductor device with a slotted metal test pad to prevent lift-off during wafer scribing.
  12. Keiji Maeda JP; Shigeru Miyagawa JP, Method of coating semiconductor wafer with resin and mold used therefor.
  13. Oka, Takahiro, Method of fabricating semiconductor device.
  14. Ohtaka Shigeo (Takasaki) Andoo Akio (Gunma) Iijima Tetsuo (Takasaki JPX), Method of manufacturing semiconductor device with controlled carrier lifetime.
  15. Seki Hideo,JPX, Method of measuring electrical characteristics of semiconductor circuit in wafer state and semiconductor device for the.
  16. Devereaux Kevin M. (Boise ID) Bunn Mark (Boise ID) Higgins Brian (Boise ID), Method of testing individual dies on semiconductor wafers prior to singulation.
  17. Budnaitis John J. ; Leong Jimmy, Method of wafer level burn-in.
  18. Love David G. (Pleasanton CA), Module test card.
  19. Shibata Junichiro (Urawa JPX) Marumo Hiroshi (Kofu JPX) Sasamoto Gakuji (Enzan JPX), Probe apparatus.
  20. Yamada Masayuki (Nirasaki JPX), Probe apparatus.
  21. Yamaguchi Masao (Tokyo JPX), Probe apparatus.
  22. Shigeyuki Maruyama JP, Probe card with rigid base having apertures for testing semiconductor device, and semiconductor device test method using probe card.
  23. Yoshizawa Tetsuo (Yokohama JPX) Imaizumi Masaaki (Tokyo JPX) Nishida Hideyuki (Kawasaki JPX) Kondo Hiroshi (Ohsaka JPX) Sakaki Takashi (Tokyo JPX) Ichida Yasuteru (Machida JPX) Konishi Masaki (Ebina , Probe method for measuring part to be measured by use thereof and electrical circuit member.
  24. Tada Tetsuo (Hyogo JPX) Takagi Ryoichi (Hyogo JPX) Kohara Masanobu (Hyogo JPX), Probing plate for wafer testing.
  25. Mikio Ohtaki JP, Semiconductor device test apparatus.
  26. Umehara Norito,JPX ; Amagai Masazumi,JPX, Semiconductor device, manufacturing method thereof, and insulating substrate for same.
  27. Hamaguchi Tsuneo,JPX ; Kagata Kenji,JPX ; Izuta Goro,JPX ; Ishizaki Mitsunori,JPX ; Hayashi Osamu,JPX ; Hoshinouchi Susumu,JPX, Semiconductor device, production method therefor, method for testing semiconductor elements, test substrate for the meth.
  28. Nakata Yoshirou,JPX ; Yamada Toshio,JPX ; Fujiwara Atsushi,JPX ; Miyanaga Isao,JPX ; Hashimoto Shin,JPX ; Uraoka Yukiharu,JPX ; Okuda Yasushi,JPX ; Hatada Kenzou,JPX, Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe t.
  29. Nakata Yoshirou,JPX ; Yamada Toshio,JPX ; Fujiwara Atsushi,JPX ; Miyanaga Isao,JPX ; Hashimoto Shin,JPX ; Uraoka Yukiharu,JPX ; Okuda Yasushi,JPX ; Hatada Kenzou,JPX, Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and .
  30. Mignardi Michael A. (Dallas TX) Ng Laurinda (Plano TX) Croff Ronald S. (Allen TX) McKenna Robert (Houston TX) Dyer Lawrence D. (Richardson TX), Separation of wafer into die with wafer-level processing.
  31. Miyaji Naomi,JPX ; Moriya Susumu,JPX ; Maruyama Shigeyuki,JPX ; Haseyama Makoto,JPX ; Fukaya Futoshi,JPX, Test board and a test method using the same providing improved electrical connection.
  32. Jitsumori Kenro,JPX ; Furumoto Kenji,JPX ; Tanaka Shoichi,JPX ; Nakayama Tomoyuki,JPX ; Mai Mikiya,JPX ; Murayama Tugio,JPX, Testing Board.
  33. Nakata Yoshiro,JPX ; Oki Shinichi,JPX, Wafer burn-in cassette and method of manufacturing probe card for use therein.

이 특허를 인용한 특허 (3)

  1. Hebig, Travis R.; Kuczynski, Joseph; Nickel, Steven R., Implementing low temperature wafer test.
  2. Ohtaki, Mikio, Method of testing circuit elements on a semiconductor wafer.
  3. Christo, Michael Anthony; Maldonado, Julio Alejandro; Weekly, Roger Donell; Zhou, Tingdong, Silicon interposer testing for three dimensional chip stack.
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