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An apparatus, method, and system for providing dc offset reduction in a communications channel include a feedback loop to generate dc offset correction signals, which in turn are combined with an input analog signal and a processed digital signal thereby reducing dc offset. Each feedback loop may i

An apparatus, method, and system for providing dc offset reduction in a communications channel include a feedback loop to generate dc offset correction signals, which in turn are combined with an input analog signal and a processed digital signal thereby reducing dc offset. Each feedback loop may include an adaptive filter. At least one feedback loop may be responsive to an error signal that represents the difference between the delayed input of a first detector, and its output. Further, the dc offset correction signal, partially delayed, may be added to the error signal, thereby improving the response time of the dc offset correction loop.

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I claim: 1. An apparatus for removing dc offset from a digital signal, the apparatus comprising: a first detector responsive to a corrected digital signal, wherein the first detector provides a first output comprising binary signals and a second output comprising a substantially error free detector

I claim: 1. An apparatus for removing dc offset from a digital signal, the apparatus comprising: a first detector responsive to a corrected digital signal, wherein the first detector provides a first output comprising binary signals and a second output comprising a substantially error free detector input; a circuit to produce an error signal, wherein the error signal is the difference between the second output and the sum of an uncorrected digital signal and a dc offset correction signal, wherein the uncorrected digital signal is delayed by a first amount, and wherein the dc offset correction signal is delayed by a second amount; and a dc offset correction feedback loop responsive to a first loop input and a second loop input, the dc offset correction feedback loop further comprising a loop filter; wherein the dc offset correction signal is the output of the dc offset correction feedback loop, wherein the first loop input is the error signal, wherein the second loop input is one of the corrected digital signal, the uncorrected digital signal, or the first output, and wherein the dc offset correction signal is added to the digital signal to provide the corrected digital signal. 2. The apparatus of claim 1, wherein the first detector comprises a Viterbi detector. 3. The apparatus of claim 1, wherein the first detector comprises an FIR filter. 4. The apparatus of claim 1, further comprising a selector coupled to the second loop input for selecting one of the corrected digital signal, the uncorrected digital signal, or the first output. 5. The apparatus of claim 1, wherein the loop filter comprises: a first gain adjustment circuit to multiply the first loop input to produce a first product; a second gain adjustment circuit to multiply the second loop input to produce a second product; a third gain adjustment circuit to multiply the output of the dc offset correction feedback loop to produce a third product; an adder to add the first, second, and third products; and an accumulator responsive to the output from the adder to generate the output of the dc offset correction feedback loop. 6. The apparatus of claim 1, further comprising: a second detector responsive to the corrected digital signal, wherein the second detector provides a third output comprising binary signals and a fourth output comprising the substantially error free detector input, wherein the second loop input is one of the corrected digital signal, the uncorrected digital signal, the first output, the second output, the third output, or the fourth output. 7. The apparatus of claim 6, wherein the second detector comprises a simple detector. 8. The apparatus of claim 6, wherein the second detector comprises an FIR filter. 9. The apparatus of claim 6, further comprising a selector coupled to the second loop input for selecting one of the corrected digital signal, the uncorrected digital signal, the first output, the third output, or the fourth output. 10. A system for removing dc offset from a digital signal, the system comprising: at least one disk having a surface for storing data thereon; at least one transducing head for reading information recorded in data tracks on the at least one disk; a servo actuator for positioning the at least one transducing head; a communications channel for transmitting the data to and from the at least one transducing head, the communications channel providing an input signal related to the digital signal; and the apparatus of claim 1. 11. The system of claim 10, wherein the first detector comprises a Viterbi detector. 12. The system of claim 10, wherein the first detector comprises an FIR filter. 13. The system of claim 10, further comprising a selector coupled to the second loop input for selecting one of the corrected digital signal, the uncorrected digital signal, or the first output. 14. The system of claim 10, wherein the loop filter comprises: a first gain adjustment circuit to multiply the first loop input to produce a first product; a second gain adjustment circuit to multiply the second loop input to produce a second product; a third gain adjustment circuit to multiply the output of the dc offset correction feedback loop to produce a third product; an adder to add the first, second, and third products; and an accumulator responsive to the output from the adder to generate the output of the dc offset correction feedback loop. 15. The system of claim 10 further comprising: a second detector responsive to the corrected digital signal, wherein the second detector provides a third output comprising binary signals and a fourth output comprising a substantially error free detector input, wherein the second loop input is the corrected digital signal, the uncorrected digital signal, the first output, the third output, or the fourth output. 16. The system of claim 15, wherein the second detector comprises a simple detector. 17. The system of claim 15, wherein the second detector comprises an FIR filter. 18. The system of claim 15, further comprising a selector coupled to the second loop input for selecting one of the corrected digital signal, the uncorrected digital signal, the first output, the second output, the third output, or the fourth output. 19. The system of claim 15, wherein the data tracks on the disk contain data stored by perpendicular recording, and wherein the at least one transducing head reproduces the perpendicularly-recorded data. 20. The system of claim 19, wherein the dc offset results from the perpendicular recording. 21. An apparatus for removing dc offset from a digital signal, the apparatus comprising: a first detector means responsive to a corrected digital signal, wherein the first detector provides a first output comprising binary signals and a second output comprising a substantially error free detector input; a means to produce an error signal, wherein the error signal is the difference between the second output and the sum of an uncorrected digital signal and a dc offset correction signal, wherein the uncorrected digital signal is delayed by a first amount, and wherein the dc offset correction signal is delayed by a second amount; and a feedback means responsive to a first loop input and a second loop input, the feedback means further comprising a filtering means; wherein the dc offset correction signal is the output of the feedback means, wherein the first loop input is the error signal, wherein the second loop input is the corrected digital signal, the uncorrected digital signal, or the first output, and wherein the dc offset correction signal is added to the digital signal to provide the corrected digital signal. 22. The apparatus of claim 21, wherein the first detector means comprises a Viterbi detector. 23. The apparatus of claim 21, wherein the first detector means comprises an FIR filter. 24. The apparatus of claim 21, further comprising a selector means coupled to the second loop input for selecting one of the corrected digital signal, the uncorrected digital signal, or the first output. 25. The apparatus of claim 21, wherein the loop filtering means comprises: a first gain adjusting means to multiply the first loop input to produce a first product; a second gain adjusting means to multiply the second loop input to produce a second product; a third gain adjusting means to multiply the output of the dc offset correction feedback loop to produce a third product; an adding means to add the first, second, and third products; and an accumulator means responsive to the output from the adding means to generate the output of the feedback means. 26. The apparatus of claim 21 further comprising: a second detector means responsive to the corrected digital signal, wherein the second detector means provides a third output comprising binary signals and a fourth output comprising a substantially error free detector input, wherein the second loop input is one of the corrected digital signal, the uncorrected digital signal, the first output, the second output, the third output, or the fourth output. 27. The apparatus of claim 26, wherein the second detector means comprises a simple detector. 28. The apparatus of claim 26, wherein the second detector means comprises an FIR filter. 29. The apparatus of claim 26, further comprising selector means coupled to the second loop input for selecting one of the corrected digital signal, the uncorrected digital signal, the first output, the third output, or the fourth output. 30. A system for removing dc offset from a digital signal, the system comprising: means for storing data on a rotating disk, said means for storing data having at least one transducing head for reading information recorded in data tracks on the rotating disk; means for positioning the at least one transducing head; means for transmitting data to and from the at least one transducing head, said means for transmitting data providing an input signal; means for receiving the input signal and for providing a digital signal; and the apparatus of claim 21. 31. The system of claim 30, wherein the first detector means comprises a Viterbi detector. 32. The system of claim 30, wherein the first detector means comprises an FIR filter. 33. The system of claim 30, further comprising a selector means coupled to the second loop input for selecting one of the corrected digital signal, the uncorrected digital signal, or the first output. 34. The system of claim 30, wherein the loop filtering means comprises: a first gain adjusting means to multiply the first loop input to produce a first product; a second gain adjusting means to multiply the second loop input to produce a second product; a third gain adjusting means to multiply the output of the dc offset correction feedback loop to produce a third product; an adding means to add the first, second, and third products; and an accumulator means responsive to the output from the adding means to generate the output of the feedback means. 35. The system of claim 30 further comprising: a second detector means responsive to the corrected digital signal, wherein the second detector means provides a third output comprising binary signals and a fourth output comprising a substantially error free detector input, wherein the second loop input is the corrected digital signal, the uncorrected digital signal, the first output, the second output, the third output, or the fourth output. 36. The system of claim 35, wherein the second detector means comprises a simple detector. 37. The system of claim 35, wherein the second detector means comprises an FIR filter. 38. The system of claim 35, further comprising selector means coupled to the second loop input for selecting one of the corrected digital signal, the uncorrected digital signal, the first output, the second output, the third output, or the fourth output. 39. The system of claim 30, wherein the data tracks on the disk contain data stored by perpendicular recording, and wherein the at least one transducing head reproduces the perpendicularly-recorded data. 40. The system of claim 39, wherein the dc offset results from the perpendicular recording. 41. A method for removing dc offset from a digital signal, the method comprising: processing a corrected digital signal to provide a first output comprising binary signals and a second output comprising a substantially error free detector input; generating an error signal by subtracting the sum of an uncorrected digital signal and a dc offset correction signal from the second output, wherein the uncorrected digital signal is delayed by a first amount, and wherein the dc offset correction signal is delayed by a second amount; generating the dc offset correction signal responsive to the sum of a first loop input and a second loop input; and adding the dc offset correction signal to the digital signal thereby removing dc offset from the digital signal and generating the corrected digital signal, wherein the first loop input is the error signal, and wherein the second loop input is one of the corrected digital signal, the uncorrected digital signal, or the first output. 42. The method of claim 41, wherein processing the corrected digital signal comprises detecting the corrected digital signal using a Viterbi detector. 43. The method of claim 41, wherein processing the corrected digital signal comprises filtering the corrected digital signal using an FIR filter. 44. The method of claim 41, further comprising selecting one of the corrected digital signal, the uncorrected digital signal, or the first output as the second loop input. 45. The method of claim 41, wherein generating the dc offset signal further comprises: multiplying the first loop input by a first constant to produce a first product; multiplying the second loop input by a second constant to produce a second product; adding the first product to the second product to produce a sum; delaying the sum; multiplying the delayed sum by a third constant to produce a third product; and adding the first, second, and third products thereby generating the dc offset correction signal. 46. The method of claim 41 further comprising: further processing the corrected digital signal to provide a third output and a fourth output; wherein the second loop input is one of the corrected digital signal, the uncorrected digital signal, the first output, the third output, or the fourth output. 47. The method of claim 46, wherein further processing the corrected digital signal comprises detecting the corrected digital signal using a simple detector. 48. The method of claim 46, wherein further processing the corrected digital signal comprises filtering the corrected digital signal using an FIR filter. 49. The method of claim 46, further comprising selecting one of the corrected digital signal, the uncorrected digital signal, the first output, the second output, the third output, or the fourth output as the second loop input. 50. A method of removing dc offset from a digital signal in a disk drive, the method comprising: storing data in data tracks on a rotating disk by positioning at least one transducing head over the disk; transmitting data to and from the at least one transducing head to provide a digital signal; and the method of claim 41. 51. The method of claim 50, wherein the storing comprises perpendicular recording of the data in the data tracks. 52. The method of claim 51, wherein the dc offset results from the perpendicular recording. 53. A computer program product comprising a computer readable medium containing program code for performing the method of claim 41. 54. A computer program product comprising a computer readable medium containing program code for performing the method of claim 44. 55. A computer program product comprising a computer readable medium containing program code for performing the method of claim 45. 56. A computer program product comprising a computer readable medium containing program code for performing the method of claim 46. 57. A computer program product comprising a computer readable medium containing program code for performing the method of claim 49.