대표
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The invention claimed is: 1. A method, comprising: forming a channel layer over at least a portion of a substrate, wherein said channel layer substantially comprises zinc indium oxide; depositing a first material over at least a portion of a substrate by use of one or more low temperature processes to form a first portion of a dielectric layer, at least a portion of said first portion of the dielectric layer comprising inorganic dielectric material; depositing a second material over and/or in contact with said first portion of the dielectric layer by us...
The invention claimed is: 1. A method, comprising: forming a channel layer over at least a portion of a substrate, wherein said channel layer substantially comprises zinc indium oxide; depositing a first material over at least a portion of a substrate by use of one or more low temperature processes to form a first portion of a dielectric layer, at least a portion of said first portion of the dielectric layer comprising inorganic dielectric material; depositing a second material over and/or in contact with said first portion of the dielectric layer by use of one or more solution processes to form a second portion of the dielectric layer, at least a portion of said second portion of the dielectric layer comprising organic dielectric material, such as to form at least a portion of a thin film transistor (TFT). 2. The method of claim 1, wherein said first portion of the dielectric layer is formed in contact with at least a portion of said channel layer. 3. The method of claim 1, and further comprising forming a gate electrode over and/or in contact with at least a portion of said second portion of the dielectric layer. 4. The method of claim 3, and further comprising forming a source electrode and a drain electrode over at least a portion of the substrate. 5. The method of claim 4, and further comprising post-processing at least a portion of said first portion of the dielectric layer, said second portion of the dielectric layer, said channel layer, said source and drain electrodes, and/or said gate electrode. 6. The method of claim 5, wherein said post-processing comprises one or more of the following: an annealing process and an ultraviolet (UV) curing process. 7. The method of claim 6, wherein said post-processing is performed after the deposition of a particular dielectric layer, but prior to the deposition of one or more subsequent dielectric layers. 8. The method of claim 4, and further comprising: patterning at least a portion of said source and drain electrodes, said channel layer, said first portion of the dielectric layer, said second portion of the dielectric layer and/or said gate electrode. 9. The method of claim 4, wherein said channel layer is formed on said substrate, said source and drain electrodes are formed on at least a portion of said substrate and/or said channel layer, said first portion of the dielectric layer is formed on at least a portion of said channel layer and/or said source and drain electrodes, said second portion of the dielectric layer is formed on at least a portion of said first portion of the dielectric layer, and said gate electrode is formed on at least a portion of said second portion of the dielectric layer, such as to form at least a portion of a top gate thin film transistor. 10. The method of claim 4, wherein said gate electrode is formed on said substrate, said second portion of the dielectric layer is formed on at least a portion of said gate electrode and/or said substrate, said first portion of the dielectric layer is formed on at least a portion of said second portion of the dielectric layer, said source and drain electrodes are formed on at least a portion of said second portion of the dielectric layer, and said channel layer is formed on at least a portion of said second portion of the dielectric layer and/or said source and drain electrodes, such as to form at least a portion of a bottom gate thin film transistor. 11. The method of claim 1, wherein said solution processes comprise one or more of the following processes: ejection, contact printing, screen printing, dip coating, and spray coating. 12. The method of claim 11, wherein said ejection process comprises a thermal inkjet process. 13. The method of claim 4, wherein said source and drain electrodes substantially comprise indium tin oxide. 14. The method of claim 3, wherein said gate electrode substantially comprises indium tin oxide. 15. The method of claim 1, wherein said channel layer substantially comprises zinc indium oxide having a Zn:In atomic ratio approximately within the range of about 1:1 to about 1:8. 16. The method of claim 1, wherein said channel layer substantially comprises zinc indium oxide having a Zn:In atomic ratio approximately within the range of about 1:3 to about 1:5. 17. The method of claim 1, wherein said inorganic dielectric material comprises one or more of the following: AlOx, SiOx, SiNk, SiOxNy, ZrOx, TaOx, HfOx and combinations thereof. 18. The method of claim 1, wherein said wherein said organic dielectric material comprises one or more of the following: UV curable monomers including UV curable acrylic monomers, acrylic polymers, thermal curable monomers, polymer solutions, melted polymer and/or oligomer solutions, poly methyl methacrylates, poly vinylphenols, benzocyclobutenes, one or more polyimides, and combinations thereof. 19. The method of claim 1, wherein said substrate comprises one or more of the following: plastics and/or one or more organic substrate materials, including polyimides (PI), polyethylene terephthalates (PET), polyethersulfones (PES), polyetherimides (PEI), polycarbonates (PC), polyethylenenaphthalates (PEN), acrylics, polymethylmethacrylates (PMMA), and combinations thereof, one or more inorganic materials, including silicon, silicon dioxide, one or more types of glass, stainless steel, metal foils, including foils of aluminum and copper, and combinations thereof. 20. The method of claim 1, wherein said one or more low temperature processes are substantially performed within a range of temperature less than approximately 300 degrees Celsius. 21. The method of claim 1, wherein said one or more low temperature processes comprises one or more of the following: vacuum deposition, including RF sputtering, DC sputtering and reactive sputtering, atomic layer deposition (ALD), and evaporation; and one or more solution processes. 22. A method of forming a thin film transistor, comprising: a step for forming a source and drain electrode over at least a portion of a substrate; a step for forming a channel layer over at least a portion of the substrate, said channel layer substantially comprising zinc indium oxide. a step for depositing a first material over at least a portion of a substrate by use of one or more steps for low temperature processing to form a first portion of a dielectric layer, at least a portion of said first material layer comprising inorganic dielectric material; a step for depositing a second material over and/or in contact with said first portion of the dielectric layer by use of one or more steps for solution processing to form a second portion of the dielectric layer, at least a portion of said second material layer comprising organic dielectric material; and a step for forming a gate electrode over and/or in contact with at least a portion of said second portion of the dielectric layer, such as to form at least a portion of a thin film transistor (TFT). 23. The method of claim 22, and further comprising: a step for patterning at least a portion of said source and drain electrodes, said channel layer, said first portion of the dielectric layer, said second portion of the dielectric layer and/or said gate electrode. 24. The method of claim 22, wherein one or more steps for low temperature processing include: vacuum deposition, including RF sputtering, DC sputtering, reactive sputtering, atomic layer deposition (ALD), and evaporation; and one or more steps for solution processing. 25. The method of claim 24, wherein said one or more steps for solution processing comprise one or more of the following: ejection, contact printing, screen printing, dip coating, and spray coating. 26. The method of claim 24, wherein said one or more steps for low temperature processing are substantially performed within a range of temperature less than approximately 300 degrees Celsius. 27. The method of claim 22, and further comprising post-processing at least a portion of said first portion of the dielectric layer, said second portion of the dielectric layer, said channel layer, said source and drain electrodes, and/or said gate electrode by use of at least one annealing process and/or ultraviolet (UV) curing process. 28. The method of claim 22, wherein said source and said drain electrodes at least partially comprise indium tin oxide. 29. The method of claim 22, wherein said channel layer substantially comprises zinc indium oxide having a Zn:In atomic ratio approximately within the range of about 1:1 to about 1:8. 30. The method of claim 29, wherein said channel layer substantially comprises zinc indium oxide having a Zn:In atomic ratio approximately within the range of about 1:3 to about 1:5. 31. The method of claim 22, wherein said inorganic dielectric material comprises one or more of the following: AlOx, SiOx, SiNx, SiOxNy, ZrOx, TaOx, HfOx and combinations thereof. 32. The method of claim 22, wherein said wherein said organic dielectric material comprises one or more of the following: UV curable monomers including UV curable acrylic monomers, acrylic polymers, thermal curable monomers, polymer solutions, melted polymer and/or oligomer solutions, poly methyl methacrylates, poly vinylphenols, benzocydobutenes, one or more polyimides, and combinations thereof. 33. The method of claim 22, wherein said substrate comprises one or more of the following: plastics and/or one or more organic substrate materials, including polyimides (PI), polyethylene terephthalates (PET), polyethersulfones (PES), polyetherimides (PEI), polycarbonates (PC), polyethylenenaphthalates (PEN), acrylics, polymethylmethacrylates (PMMA), and combinations thereof, one or more inorganic materials, including silicon, silicon dioxide, one or more types of glass, stainless steel, metal foils, including foils of aluminum and copper, and combinations thereof. 34. A thin film transistor (TFT), formed substantially by a process comprising: forming a source and drain electrode over at least a portion of a substrate; forming a channel layer over at least a portion of the substrate, said channel layer substantially comprising zinc indium oxide. depositing a first material over at least a portion of a substrate by use of one or more low temperature processes to form a first portion of a dielectric layer, at least a portion of said first material layer comprising inorganic dielectric material; depositing a second material over and/or in contact with said first portion of the dielectric layer by use of one or more solution processes to form a second portion of the dielectric layer, at least a portion of said second material layer comprising organic dielectric material; and forming a gate electrode over and/or in contact with at least a portion of said second portion of a dielectric layer such that at least a portion of a thin film transistor (TFT) is formed. 35. The TFT of claim 34, wherein said source and said drain electrodes at least partially comprise indium tin oxide. 36. The TFT of claim 34, and further comprising: patterning at least a portion of said source and drain electrodes, said channel layer, said first portion of the dielectric layer, said second portion of the dielectric layer and/or said gate electrode. 37. The TFT of claim 34, wherein at least a portion of said source and drain electrodes, said channel layer, said first and said second portions of the dielectric layer and/or said gate electrode are formed by use of one or more low temperature processes. 38. The TFT of claim 37, wherein said one or more low temperature processes are substantially performed within a range of temperature less than approximately 300 degrees Celsius. 39. The TFT of claim 37, wherein one or more low temperature processes include: vacuum deposition, including RF sputtering, DC sputtering, reactive sputtering, atomic layer deposition (ALD), and evaporation; and one or more solution processes. 40. The TFT of claim 37, wherein said one or more solution processes comprise one or more of the following: ejection, contact printing, screen printing, dip coating, spray coating, screen printing, chemical bath deposition, and successive ionic layer absorption and reaction. 41. The TFT of claim 34, wherein said one or more vacuum deposition processes comprise one or more of the following: sputtering, including RF sputtering; atomic layer deposition (ALD); and evaporation. 42. The TFT of claim 34, and further comprising post-processing at least a portion of said first portion of the dielectric layer, said second portion of the dielectric layer, said channel layer, said source and drain electrodes, and/or said gate electrode by use of at least one annealing process and/or ultraviolet (UV) curing process. 43. The TFT of claim 34, wherein said channel layer substantially comprises zinc indium oxide having a Zn:In atomic ratio approximately within the range of about 1:1 to about 1:8. 44. The TFT of claim 43, wherein said channel layer substantially comprises zinc indium oxide having a Zn:In atomic ratio approximately within the range of about 1:3 to about 1:5. 45. The TFT of claim 34, wherein said inorganic dielectric material comprises one or more of the following: AlOx, SiOx, SiNx, SiOxNy, ZrOx, TaOx, HfOx and combinations thereof. 46. The TFT of claim 34, wherein said wherein said organic dielectric material comprises one or more of the following: UV curable monomers including UV curable acrylic monomers, acrylic polymers, thermal curable monomers, polymer solutions, melted polymer and/or oligomer solutions, poly methyl methacrylates, poly vinylphenols, benzocyclobutenes, one or more polyimides, and combinations thereof. 47. The TFT of claim 34, wherein said substrate comprises one or more of the following: plastics and/or one or more organic substrate materials, including polyimides (PI), polyethylene terephthalates (PET), polyethersulfones (PES), polyetherimides (PEI), polycarbonates (PC), polyethylenenaphthalates (PEN), acrylics including polymethylmethacrylates (PMMA), and combinations thereof, one or more inorganic materials, including silicon, silicon dioxide, one or more types of glass, stainless steel, metal foils, including foils of aluminum and copper, and combinations thereof.
