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Programmable lookup table with dual input and output terminals in RAM mode

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/173
출원번호 US-0152736 (2005-06-14)
등록번호 US-7265576 (2007-09-04)
발명자 / 주소
  • Kondapalli,Venu M.
  • Bauer,Trevor J.
  • Chirania,Manoj
  • Costello,Philip D.
  • Young,Steven P.
출원인 / 주소
  • Xilinx, Inc.
인용정보 피인용 횟수 : 12  인용 특허 : 66

초록

A programmable lookup table optionally provides two input signals and two output signals to an interconnect structure of a programmable integrated circuit when programmed to function as a random access memory (RAM). An integrated circuit includes an interconnect structure and a N-input lookup table

대표청구항

What is claimed is: 1. An integrated circuit, comprising: an interconnect structure; and an N-input lookup table (LUT) having exactly N LUT input terminals coupled to the interconnect structure, and further having first and second LUT output terminals, wherein N is an integer, wherein the LUT is co

이 특허에 인용된 특허 (66)

  1. Subramani Kengeri, 2T dual-port DRAM in a pure logic process with non-destructive read capability.
  2. Pedersen, Bruce, Automated implementation of non-arithmetic operators in an arithmetic logic cell.
  3. Crotty, Patrick J.; Pi, Tao; Young, Steven P., Carry logic design having simplified timing modeling for a field programmable gate array.
  4. Lo, William, Circuit for reducing pin count of a semiconductor chip and method for configuring the chip.
  5. Chaudhary,Kamal; Krishnamurthy,Sridhar, Circuits and methods for testing programmable logic devices using lookup tables and carry chains.
  6. Cliff Richard G., Coarse-grained look-up table architecture.
  7. Kenneth D. Chapman GB; Steven P. Young, Configurable logic block with AND gate for efficient multiplication in FPGAS.
  8. Chapman, Kenneth D.; Young, Steven P., Configurable logic block with and gate for efficient multiplication in FPGAS.
  9. Young Steven P. ; Bapat Shekhar ; Chaudhary Kamal ; Bauer Trevor J. ; Iwanczuk Roman, Configurable logic element with ability to evaluate five and six input functions.
  10. Young Steven P. ; Bapat Shekhar ; Chaudhary Kamal ; Bauer Trevor J. ; Iwanczuk Roman, Configurable logic element with ability to evaluate wide logic functions.
  11. Bernard J. New ; Ralph D. Wittig ; Sundararajarao Mohan, Configurable logic element with expander structures.
  12. New, Bernard J.; Wittig, Ralph D.; Mohan, Sundararajarao, Configurable logic element with expander structures.
  13. Young Steven P. ; New Bernard J. ; Camilleri Nicolas John ; Bauer Trevor J. ; Bapat Shekhar ; Chaudhary Kamal ; Krishnamurthy Sridhar, Configurable logic element with fast feedback paths.
  14. Ralph D. Wittig ; Sundararajarao Mohan ; Bernard J. New, Configurable lookup table for programmable logic devices.
  15. Steven P. Young, Expandable interconnect structure for FPGAS.
  16. Young Steven P. ; New Bernard J. ; Camilleri Nicolas John ; Bauer Trevor J. ; Bapat Shekhar ; Chaudhary Kamal ; Krishnamurthy Sridhar, FPGA CLE with two independent carry chains.
  17. Bauer Trevor J. ; Young Steven P., FPGA architecture with deep look-up table RAMs.
  18. Bauer Trevor J. ; Young Steven P., FPGA architecture with dual-port deep look-up table RAMS.
  19. Bauer Trevor J. ; Young Steven P., FPGA architecture with wide function multiplexers.
  20. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., FPGA configurable logic block with multi-purpose logic/memory circuit.
  21. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., FPGA configurable logic block with multi-purpose logic/memory circuit.
  22. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., FPGA configurable logic block with multi-purpose logic/memory circuit.
  23. Britton Barry K. (Schnecksville PA) Hill Dwight D. (San Carlos CA), FPGA having PFU with programmable output driver inputs.
  24. Chaudhary Kamal, FPGA having logic element carry chains capable of generating wide XOR functions.
  25. Bauer Trevor J. ; Young Steven P., FPGA interconnect structure with high-speed high fanout capability.
  26. Ralph D. Wittig ; Sundararajarao Mohan ; Bernard J. New, FPGA logic element with variable-length shift register capability.
  27. Trevor J. Bauer ; Steven P. Young ; Richard A. Carberry, FPGA lookup table with dual ended writes for ram and shift register modes.
  28. Carberry, Richard A.; Young, Steven P.; Bauer, Trevor J., FPGA lookup table with high speed read decorder.
  29. Pi, Tao; Crotty, Patrick J., FPGA lookup table with transmission gate structure for reliable low-voltage operation.
  30. Young Steven P. ; Bauer Trevor J. ; Chaudhary Kamal ; Krishnamurthy Sridhar, FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines.
  31. Young Steven P. ; Chaudhary Kamal ; Bauer Trevor J., FPGA repeatable interconnect structure with hierarchical interconnect lines.
  32. New Bernard I. (Los Gatos CA) Young Steven P. (San Jose CA), Fast carry structure with synchronous input.
  33. Lewis, David; Pedersen, Bruce; Kaptanoglu, Sinan; Lee, Andy, Fracturable lookup table and logic element.
  34. Nakaya, Shogo, Function block.
  35. Betz, Vaughn; Rose, Jonathan, Heterogeneous interconnection architecture for programmable logic devices.
  36. Jones Christopher W. ; Marshall Jeffery Mark, High performance product term based carry chain scheme.
  37. Alireza S. Kaviani, Implementing wide multiplexers in an FPGA using a horizontal chain structure.
  38. Lee,Andy L.; Ngo,Ninh; Betz,Vaughn; Lewis,David; Pedersen,Bruce; Schleicher,James, Initializing a carry chain in a programmable logic device.
  39. Percey Andrew K. ; Bauer Trevor J. ; Young Steven P., Input/output interconnect circuit for FPGAs.
  40. Pierce Kerry M. ; Erickson Charles R. ; Huang Chih-Tsung ; Wieland Douglas P., Interconnect architecture for field programmable gate array using variable length conductors.
  41. Steven P. Young ; Kamal Chaudhary ; Trevor J. Bauer, Interconnect structure for a programmable logic device.
  42. Lewis,David; Schleicher,James, LUT-based logic element with support for Shannon decomposition and associated method.
  43. McGettigan Edward S., Loadable up-down counter with asynchronous reset.
  44. Mendel David W. ; Cliff Richard G., Logic element for a programmable logic integrated circuit.
  45. New Bernard J., Logic structure and circuit for fast carry.
  46. Ralph D. Wittig ; Sundararajarao Mohan ; Richard A. Carberry, Logic/memory circuit having a plurality of operating modes.
  47. New Bernard J., Look-ahead carry structure with homogeneous CLB structure and pitch larger than CLB pitch.
  48. Bauer Trevor J., Lookup tables which double as shift registers.
  49. New Bernard J. (Los Gatos CA), Method and structure for providing fast propagation of a carry signal in a field programmable gate array.
  50. McGettigan Edward S. ; Tran Jennifer T. ; Goetting F. Erich, Method for design implementation of routing in an FPGA using placement directives such as local outputs and virtual buffers.
  51. Wittig Ralph D. ; Mohan Sundararajarao, Method for implementing large multiplexers with FPGA lookup tables.
  52. Chaudhary Kamal, Method for implementing priority encoders using FPGA carry logic.
  53. Cliff, Richard G.; Heile, Francis B.; Huang, Joseph; Mendel, David W.; Pendersen, Bruce B.; Sung, Chiakang; Veenstra, Kerry; Wang, Bonnie I., PCI-compatible programmable logic devices.
  54. Chan Andrew K. ; Birkner John M. ; Chua Hua-Thye, Programmable application specific integrated circuit and logic cell therefor.
  55. Cliff Richard G. ; Reddy Srinivas T. ; Jefferson David E. ; Raman Rina ; Cope L. Todd ; Lane Christopher F. ; Huang Joseph ; Heile Francis B. ; Pedersen Bruce B. ; Mendel David W. ; Lytle Craig S. ; , Programmable logic array integrated circuit devices.
  56. Pedersen Bruce B., Programmable logic array integrated circuits with enhanced carry routing.
  57. New Bernard J., Programmable logic device having a composable memory array overlaying a CLB array.
  58. Trimberger, Stephen M., Programmable logic device with time-multiplexed interconnect.
  59. Kaptanoglu, Sinan; Hutton, Michael D.; Schleicher, James, Programmable logic devices with bidirect ional cascades.
  60. El Ayat Khaled A. (Cupertino CA) Bakker Gregory W. (Sunnyvale CA) Lien Jung-Cheun (San Jose CA) Plants William C. (Santa Clara CA) Kaptanoglu Sinan (San Carlos CA) Gopisetty Runip (Los Gatos CA) Chan, Programmable logic module and architecture for field programmable gate array device.
  61. Ochotta Emil S. ; Wieland Douglas P., Routing architecture using a direct connect routing mesh.
  62. Morse, Douglas C.; Lee, Clement, Structure and method for implementing wide multiplexers.
  63. Bauer Trevor J. ; Newgard Bruce A. ; Allaire William E. ; Young Steven P., Structure for optionally cascading shift registers.
  64. Goetting,F. Erich; Jennings,John K.; Collins,Anthony J.; Quinn,Patrick J., System monitor in a programmable logic device.
  65. Om P. Agrawal ; Herman M. Chang ; Bradley A. Sharpe-Geisler ; Giap H. Tran, Variable grain architecture for FPGA integrated circuits.
  66. Lewis, David M.; Leventis, Paul; Lee, Andy L.; Kim, Henry; Pedersen, Bruce; Wysocki, Chris; Lane, Christopher F.; Marquardt, Alexander; Santurkar, Vikram; Betz, Vaughn, Versatile logic element and logic array block.

이 특허를 인용한 특허 (12)

  1. Birkner, John; Chan, Andrew Ka Lab, FPGA having low power, fast carry chain.
  2. Camarota, Rafael C., Flexible sized die for use in multi-die integrated circuit.
  3. Fan, Yuezhen; Thorne, Eric J.; Li, Xiao-Yu; O'Rourke, Glenn; Trimberger, Stephen M., Increased usable programmable device dice.
  4. Bauer, Trevor J.; Lindholm, Jeffrey V.; Goetting, F. Erich; Talley, Bruce E.; Tanikella, Ramakrishna K.; Young, Steven P., Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies.
  5. Bauer,Trevor J.; Lindholm,Jeffrey V.; Goetting,F. Erich; Talley,Bruce E.; Tanikella,Ramakrishna K.; Young,Steven P., Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies.
  6. Goetting,F. Erich; Bauer,Trevor J.; McGuire,Patrick J.; Talley,Bruce E.; Wu,Paul Ying Fung; Young,Steven P., Methods of providing a family of related integrated circuits of different sizes.
  7. Pang,Raymond C.; Bauer,Trevor J.; Goetting,F. Erich; Talley,Bruce E.; Young,Steven P., Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes.
  8. Camarota, Rafael C., Monolithic integrated circuit die having modular die regions stitched together.
  9. Hisamura, Toshiyuki, Oversized interposer.
  10. Camarota, Rafael C., Oversized interposer formed from a multi-pattern region mask.
  11. Hisamura, Toshiyuki, Single mask set used for interposer fabrication of multiple products.
  12. Young,Steven P.; Bauer,Trevor J.; Goetting,F. Erich; Lamarche,P. Hugo; McGuire,Patrick J.; Oh,Kwansuhk; Pang,Raymond C.; Talley,Bruce E.; Wu,Paul Ying Fung, Yield-enhancing methods of providing a family of scaled integrated circuits.
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