초록 ▼

A method and an apparatus for retiming in a network of multiple context processing elements in a network of multiple context processing elements are provided. A programmable delay element is configured to programmably delay signals between a number of multiple context processing elements of an array

A method and an apparatus for retiming in a network of multiple context processing elements in a network of multiple context processing elements are provided. A programmable delay element is configured to programmably delay signals between a number of multiple context processing elements of an array without requiring a multiple context processing element to implement the delay. The output of a first multiple context processing element is coupled to a first multiplexer and to the input of a number of serially connected delay registers. The output of each of the serially connected registers is coupled to the input of a second multiplexer. The output of the second multiplexer is coupled to the input of the first multiplexer, and the output of the first multiplexer is coupled to a second multiple context processing element. The first and second multiplexers are provided with at least one set of data representative of at least one configuration memory context of a multiple context processing element. The first and second multiplexers are controlled to select one of a number of delay durations in response to the received set of data. A delay is programmed in the network structure in response to a data type being transferred between particular multiple context processing elements.

대표청구항 ▼

The invention claimed is: 1. A method for retiming an array of processing elements, the method comprising: programming a delay using a multiplexer and a clocked delay circuit in response to a configuration memory context of a processing element, wherein the multiplexer and the clocked delay circuit

The invention claimed is: 1. A method for retiming an array of processing elements, the method comprising: programming a delay using a multiplexer and a clocked delay circuit in response to a configuration memory context of a processing element, wherein the multiplexer and the clocked delay circuit are coupled among a plurality of processing elements, and the delay is programmed with data representative of a configuration memory context; coupling the output of a first processing element to a first multiplexer and to the input of a plurality of serially connected delay registers; coupling the output of each of the plurality of serially connected delay registers to the input of a second multiplexer, the output of the second multiplexer coupled to the input of the first multiplexer; and coupling the output of the first multiplexer to a second processing element. 2. The method of claim 1, wherein programming the delay further comprises: providing the first and second multiplexers with data representative of a configuration memory context of a processing element; and controlling the first and second multiplexers to select one of a plurality of delay durations in response to the representative data. 3. A method for retiming an array of processing elements, the method comprising: programming a delay using a multiplexer and a clocked delay circuit in response to a configuration memory context of a processing element, wherein the multiplexer and the clocked delay circuit are coupled among a plurality of processing elements, and the delay is programmed with data representative of a configuration memory context; assigning virtual identifications to a plurality of processing elements; transmitting data to at least one of the plurality of processing elements, the data comprising an address mask; comparing the virtual identification of each of the plurality of processing elements masked with the address mask to a masked destination identification; and when the masked virtual identification of a processing element matches the masked destination identification, manipulating at least one of the plurality of processing elements in response to the transmitted data, the at least one of the manipulated processing elements defining at least one region of the array. 4. An apparatus for providing retiming in an array of processing elements, the apparatus comprising: a configuration memory for storing a configuration memory context for controlling interconnection of the processing elements and storing information representing data types being transferred among the processing elements; a plurality of delay circuits coupled among processing elements, the plurality of delay circuits including at least one clocked delay circuit; and a multiplexer coupled to a clocked delay circuit of the at least one clocked delay circuit, the multiplexer selecting a delay circuit from the plurality of delay circuits in response to the configuration memory context, wherein the delay is programmed in response to the stored information representing data types being transferred among the processing elements, and wherein the delay circuit is selected independent of the execution time of a previous instruction. 5. The apparatus of claim 4, wherein the delay circuit comprises a delay register. 6. The apparatus of claim 5, wherein the delay register comprises a latch. 7. An apparatus for providing retiming in an array of processing elements, the apparatus comprising: a clocked delay circuit coupled among processing elements; and a multiplexer coupled to the clocked delay circuit, the multiplexer selecting a delay duration in response to a configuration memory context of a processing element, the delay programmed in response to a data type being transferred among the processing elements; an output of a first processing element is coupled to a first multiplexer and to an input of a plurality of serially connected delay registers, wherein the clocked delay circuit comprises a plurality of serially connected delay registers, and wherein an output of each of the plurality of serially connected delay registers is coupled to an input of a second multiplexer, an output of the second multiplexer is coupled to an input of the first multiplexer; and an output of the first multiplexer is coupled to a second processing element. 8. The apparatus of claim 7, wherein the first and second multiplexers are provided with data representative of at least one configuration memory context of a processing element; and the first and second multiplexers are controlled to select one of a plurality of delay durations in response to the representative data. 9. A method for retiming an array of processing elements, the method comprising: storing configuration data in a configuration memory for controlling interconnection of the processing elements in the array of processing elements; storing information in the configuration memory representing data types being transferred among the processing elements; and programming a delay element selected from a plurality of delay elements, the selected delay element being configured to programmably delay signals among a plurality of processing elements of the array of processing elements without requiring a processing element to implement the delay, wherein the delay is programmed with the stored information representing data types being transferred among the processing elements, and wherein the element comprises at least one delay register, the method further comprising: programming a delay using at least one multiplexer and the at least one delay register in response to a configuration memory context of a processing element, the at least one multiplexer and the at least one delay register being coupled between a plurality of processing elements. 10. The method of claim 9, wherein the array of processing elements comprises a networked array of processing elements. 11. The method of claim 9, wherein the array of processing elements comprises an array of multiple context processing elements. 12. The method of claim 11, wherein the array of multiple context processing elements comprises a networked array of processing elements. 13. A method for retiming an array of processing elements, the method comprising: using a programmable clocked delay element configured to programmably delay signals among a plurality of processing elements without requiring a processing element to implement the delay, wherein the delay is programmed with data representative of a configuration memory context; programming a delay using at least one multiplexer and at least one delay register of the programmable clocked delay element in response to a configuration memory context of a processing element, the at least one multiplexer and the at least one delay register coupled between a plurality of processing elements; providing first and second multiplexers with data representative of a configuration memory context of a processing element; and controlling the first and second multiplexers to select one of a plurality of delay durations in response to the representative data.