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Non-volatile memory and method with bit line to bit line coupled compensation

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-016/04
출원번호 US-0422034 (2006-06-02)
등록번호 US-7269069 (2007-09-11)
발명자 / 주소
  • Cernea,Raul Adrian
  • Li,Yan
  • Mofidi,Mehrdad
  • Khalid,Shahzad
출원인 / 주소
  • SanDisk Corporation
대리인 / 주소
    Davis Wright Tremaine LLP
인용정보 피인용 횟수 : 13  인용 특허 : 57

초록

When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention pr

대표청구항

It is claimed: 1. In a non-volatile memory having an array of memory storage units, each unit having a charge storage unit between a control gate and a channel region defined by a source and a drain, and a bit line switchably coupled to the drain, a method of programming a page of memory storage un

이 특허에 인용된 특허 (57)

  1. Maayan, Eduardo; Sofer, Yair; Eliyahu, Ron; Eitan, Boaz, Architecture and scheme for a non-strobed read sequence.
  2. Yamamoto, Kaoru; Ito, Nobuhiko, BIT LINE CONTROL DECODER CIRCUIT, VIRTUAL GROUND TYPE NONVOLATILE SEMICONDUCTOR STORAGE DEVICE PROVIDED WITH THE DECODER CIRCUIT, AND DATA READ METHOD OF VIRTUAL GROUND TYPE NONVOLATILE SEMICONDUCTOR.
  3. Matsuda Yoshio (Hyogo JPX) Fujishima Kazuyasu (Hyogo JPX), Bit line structure for a dynamic type semiconductor memory device.
  4. Kim, Dae Han, Circuit for clamping word-line voltage.
  5. Yuan Jack H. (Cupertino CA) Samachisa Gheorghe (San Jose CA) Guterman Daniel C. (Fremont CA) Harari Eliyahou (Los Gatos CA), Dense vertical programmable read only memory cell structure and processes for making them.
  6. Parker Allan, Descending staircase read technique for a multilevel cell NAND flash memory device.
  7. Young Kenneth E. (Newark CA), Differential bit line clamp.
  8. Hollmer, Shane C.; Chen, Pau-Ling; Binh, Quang, Double boosting scheme for NAND to improve program inhibit characteristics.
  9. Hultberg Kent,SEX ; Ranta Teuvo,SEX ; Larsson Hans,SEX, Double-walled structure in a ventilation duct system.
  10. Shiratake Shinichiro (Tokyo JPX) Ohuchi Kazunori (Yokohama JPX) Takashima Daisaburo (Kawasaki JPX), Dynamic semiconductor memory device.
  11. Guterman Daniel C. (Fremont CA) Samachisa Gheorghe (San Jose CA) Fong Yupin K. (Fremont CA) Harrai Eliyahou (Los Gatos CA), EEPROM with split gate source side injection.
  12. Gongwer, Geoffrey S., Efficient read, write methods for multi-state memory.
  13. Harari Eliyahou (Los Gatos CA) Norman Robert D. (San Jose CA) Mehrotra Sanjay (Milpitas CA), Flash EEPROM system with erase sector select.
  14. Harari Eliyahou (2320 Friars La. Los Altos CA 94022), Highly compact EPROM and flash EEPROM devices.
  15. Tsao, Cheng-Chung; Lin, Tien-ler, Integrated circuit memory device having interleaved read and program capabilities and methods of operating same.
  16. James M. Cleeves, Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays.
  17. Wong, Sau Ching, Memory with offset bank select cells at opposite ends of buried diffusion lines.
  18. Smith Kevin B. ; Garvin P. Keith, Method and apparatus for allocating storage in a flash memory.
  19. Hsia, Steve K.; Han, Kyung Joon; Tran, Dung, Method and apparatus for multiple byte or page mode programming of a flash memory array.
  20. Beer, Peter, Method for precharging memory cells of a dynamic semiconductor memory during power-up and semiconductor memory.
  21. Choi Jung-Dal,KRX, Method for programming a non-volatile memory device with program disturb control.
  22. Yuan Jack H. (Cupertino CA), Method of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with t.
  23. Yuan Jack H. (Cupertino CA) Harari Eliyahou (Los Gatos CA), Method of making dense flash EEprom semiconductor memory structures.
  24. Daniele Vincenzo (Milan ITX) Corda Giuseppe (Saronno ITX) Magrucci Aldo (Milan ITX) Torelli Guido (Milan ITX), Method of programming an electrically alterable nonvolatile memory.
  25. Mangan, John S.; Guterman, Daniel C.; Samachisa, George; Murphy, Brian; Wang, Chi-Ming; Quader, Khandker N., Method of reducing disturbs in non-volatile memory.
  26. Morikawa Kouichi,JPX ; Ida Jiro,JPX, Multi-port semiconductor memory device with reduced coupling noise.
  27. Tanaka Tomoharu (Yokohama JPX) Hemink Gertjan (Kawasaki JPX), Multi-state EEPROM having write-verify control circuit.
  28. Mehrotra Sanjay (Milpitas CA) Harari Eliyahou (Los Gatos CA) Lee Winston (San Francisco CA), Multi-state EEprom read and write circuits and techniques.
  29. Guterman Daniel C. ; Fong Yupin Kawing, Multi-state memory.
  30. Shimizu Kazuhiro,JPX ; Satoh Shinji,JPX ; Aritome Seiichi,JPX, Non-volatile NAND type semiconductor memory device with stacked gate memory cells and a stacked gate select transistor.
  31. Khalid, Shahzad; Li, Yan; Cernea, Raul-Adrian; Mofidi, Mehrdad, Non-volatile memory and method with bit line compensation dependent on neighboring operating modes.
  32. Cernea,Raul Adrian; Li,Yan; Mofidi,Mehrdad; Khalid,Shahzad, Non-volatile memory and method with bit line coupled compensation.
  33. Cernea,Raul Adrian; Li,Yan, Non-volatile memory and method with improved sensing.
  34. Eitan Boaz,ILX, Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping.
  35. Itoh Yasuo,JPX ; Sakui Koji,JPX, Non-volatile semiconductor memory device.
  36. Endoh Tetsuo,JPX ; Tanaka Yoshiyuki,JPX ; Aritome Seiichi,JPX ; Shirota Riichiro,JPX ; Shuto Susumu,JPX ; Tanaka Tomoharu,JPX ; Hemink Gertjan,JPX ; Tanzawa Toru,JPX, Non-volatile semiconductor memory device and method of programming a non-volatile memory cell to a predetermined state.
  37. Akaogi Takao (Kawasaki JPX) Yoshida Masanobu (Kawasaki JPX) Oqawa Yasushige (Kasuqai JPX) Kasa Yasushi (Kawasaki JPX) Kawamura Shouichi (Kawasaki JPX), Nonvolatile semiconductor memory.
  38. Takeuchi Ken,JPX ; Sakui Koji,JPX ; Tanaka Tomoharu,JPX ; Aritome Seiichi,JPX, Nonvolatile semiconductor memory device.
  39. Takeuchi Ken,JPX ; Tanaka Tomoharu,JPX, Nonvolatile semiconductor memory device.
  40. Satoh Shinji,JPX ; Shirota Riichiro,JPX ; Tanzawa Toru,JPX, Nonvolatile semiconductor memory device capable of controlling mutual timing of write voltage pulse and transfer voltage pulse.
  41. Ken Takeuchi JP; Tomoharu Tanaka JP; Noboru Shibata JP, Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells.
  42. Noda Masanori,JPX ; Arase Kenshiro,JPX ; Sugiyama Toshinobu,JPX ; Naiki Ihachi,JPX, Nonvolatile semiconductor memory with fast data programming and erasing function using ECC.
  43. Cavaleri, Paola; Leconte, Bruno; Zink, Sébastien; Devin, Jean, Page-erasable flash memory.
  44. Harari Eliyahou (Los Gatos CA) Mehrotra Sanjay (Milpitas CA), Segmented column memory array.
  45. Takeuchi Ken,JPX ; Tanaka Tomoharu,JPX, Semiconductor device and memory system.
  46. Takeuchi Ken,JPX ; Tanaka Tomoharu,JPX, Semiconductor device and memory system.
  47. Himeno Toshihiko,JPX ; Kanda Kazushige,JPX ; Nakamura Hiroshi,JPX, Semiconductor memory device.
  48. Nobukata Hiromi,JPX, Semiconductor nonvolatile memory device and method of data programming the same.
  49. Byeong-Hoon Lee KR; Young-Ho Lim KR, Sense amplifier circuit for a flash memory device.
  50. Takahashi Hiroyuki (Tokyo JPX), Sense amplifier circuit implemented by bipolar transistor and improved in current consumption.
  51. Womack Richard, Sense amplifier for low read-voltage memory cells.
  52. Tran Hiep V. (1816 Woodbury Carrollton TX 75007), Sensing and decoding scheme for a BiCMOS read/write memory.
  53. Yuan Jack H. (Cupertino CA) Samachisa Gheorghe (San Jose CA), Technique of forming over an irregular surface a polysilicon layer with a smooth surface.
  54. Eitan Boaz,ILX, Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping.
  55. Brady James, Voltage clamping method and apparatus for dynamic random access memory devices.
  56. Shaw Jeng-Jye, Wrap-around mechanism for memory split-wordline read.
  57. Kai Yasuyuki (Yokohama JPX), semiconductor memory device having a flash write function.

이 특허를 인용한 특허 (13)

  1. Chandrasekhar, Uday; Helm, Mark, Memory kink checking.
  2. Chandrasekhar, Uday; Helm, Mark A., Memory kink checking.
  3. Chandrasekhar, Uday; Helm, Mark A., Memory kink checking.
  4. Chandrasekhar, Uday; Helm, Mark A., Memory kink checking.
  5. Moschiano, Violante; Roohparvar, Frankie; Santin, Giovanni; Sarin, Vishal; Vahidimowlavi, Allahyar; Vali, Tommaso, Method for kink compensation in a memory.
  6. Moschiano, Violante; Roohparvar, Frankie; Santin, Giovanni; Sarin, Vishal; Vahidimowlavi, Allahyar; Vali, Tommaso, Method for kink compensation in a memory.
  7. Moschiano, Violante; Roohparvar, Frankie; Santin, Giovanni; Sarin, Vishal; Vahidimowlavi, Allahyar; Vali, Tommaso, Method for kink compensation in a memory.
  8. Sharon, Eran, Methods for extending the effective voltage window of a memory cell.
  9. Sharon, Eran, Methods for extending the effective voltage window of a memory cell.
  10. Tamada, Satoru, Multi level inhibit scheme.
  11. Tamada, Satoru, Multi level inhibit scheme.
  12. Cernea, Raul Adrian; Li, Yan; Mofidi, Mehrdad; Khalid, Shahzad, Non-volatile memory and method with bit line to bit line coupled compensation.
  13. Kwon, Ohsuk; Choi, Kihwan, Nonvolatile memory device, program method and precharge voltage boosting method thereof, and memory system including the nonvolatile memory device.
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