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A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit

A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

대표청구항 ▼

What is claimed is: 1. A delay circuit comprising: a delay line circuit including a plurality of stages of delay units; a first switch controlled to be turned on and off based on an input control signal, and a second switch, said second switch being connected to an output of the delay unit of the s

What is claimed is: 1. A delay circuit comprising: a delay line circuit including a plurality of stages of delay units; a first switch controlled to be turned on and off based on an input control signal, and a second switch, said second switch being connected to an output of the delay unit of the stage number corresponding to said input control signal, and being turned on at a time point when the transition edge of the rise or fall of the input signal supplied to said delay circuit and propagated has traversed a number of stages corresponding to said input control signal, said second switch causing transition of a common node from one logic value to the other logic value through said first switch in the on-state; a signal generating circuit connected to said common node to generate a rising signal or a falling signal responsive to said transition of said common node; and a control circuit responsive to an input signal supplied to said delay circuit to set said common node to said one logic value by the other transition, that is, the falling or rising, of said input signal. 2. The delay circuit according to claim 1, wherein one ends of a plurality of said second switches, connected to outputs of plural delay units of respective different stages of said delay circuit so as to be on/off controlled are connected common to said common node; and wherein said first switch, supplied with said control signal and on/off controlled, is provided across the power supply and the other end of each of said plural second switches. 3. The delay circuit according to claim 1, wherein the delay unit of said delay line circuit is composed by an inverter circuit; a series circuit composed of each of said second switches connected to outputs of the odd-numbered delay units and each of said first switch associated with each of said second switches is connected to a first common node provided for odd-numbered stages; a series circuit composed of each of said second switches connected to the outputs of the even-numbered delay units and said first switch associated with each of said second switches is connected to a second common node provided for even-numbered stages; said signal generating circuit is provided for each of said first and second common nodes; and wherein the delays of the rising and falling of the output signal from the rising and falling of the input signal are varied. 4. A delay circuit comprising: a delay line circuit including a plurality of stages of delay units; a plurality of series circuits each including a switch receiving at a control terminal thereof the outputs of every preset number of odd-numbered delay units of said delay circuit and a switch receiving a control signal at a control terminal thereof, said series circuits being connected in parallel with one another across a first power supply and a first common node; a first signal generating circuit turned on when said first common node is at said second power supply potential to output a first logic level; a first control circuit for outputting a signal controlling the setting of said first common node to said second power supply potential, based on the input signal and an output of said first signal generating circuit; a plurality of series circuits each including a switch receiving at a control terminal thereof the outputs of every preset number of even-numbered delay units of said delay circuit and a switch receiving a control signal at a control terminal thereof, said series circuits being connected across said first power supply and the second common node in parallel with each other; a second signal generating circuit turned on when said second common node is at said second power supply potential to output a first logic level; and a second control circuit for outputting a signal controlling the setting of said second common node to said second power supply potential, based on the input signal and an output of said second signal generating circuit; said first and second signal generating circuits outputting a signal corresponding to a signal which has delayed the falling edge of said input signal and a signal corresponding to a signal which has delayed the rising edge of said input signal. 5. A delay circuit comprising: a delay line circuit including a plurality of stages of delay units; a plurality of series circuits each including a switch receiving at a control terminal thereof the outputs of every preset number of a first set of odd-numbered delay units of said delay line circuit and a switch receiving a control signal at a control terminal thereof, said series circuits being connected across a first power supply and the first common node in parallel with each other, a plurality of series circuits each including a switch receiving at a control terminal thereof the outputs of every preset number of a second set of odd-numbered delay units of said delay circuit and a switch receiving a control signal at a control terminal thereof, said series circuits being connected across a first power supply and the second common node in parallel with each other; a first signal generating circuit turned on when said first common node is at said second power supply potential to output a first logic level; a second signal generating circuit turned on when said second common node is at said second power supply potential to output a first logic level; a first control circuit for outputting a signal controlling the setting of said first and second common nodes to said second power supply potential, based on the input signal and outputs of said first and second signal generating circuits; a plurality of series circuits each including a switch receiving at a control terminal thereof the outputs of every preset number of a first set of even-numbered delay units of said delay circuit and a switch receiving a control signal at a control terminal thereof, said series circuits being connected across said first power supply and a third common node in parallel with each other; a plurality of series circuits each including a switch receiving at a control terminal thereof the outputs of every preset number of a second set of even-numbered delay units of said delay circuit and a switch receiving a control signal at a control terminal thereof, said series circuits connected across said first power supply and a fourth common node in parallel with each other; a third signal generating circuit turned on when said third common node is at said second power supply potential to output a second logic level; a fourth signal generating circuit turned on when said fourth common node is at said second power supply potential to output a second logic level; and a second control circuit for outputting a signal controlling the setting of said third and fourth common nodes to said second power supply potential, based on the input signal and an output of said third and fourth signal generating circuits; said first and second signal generating circuits and said third and fourth signal generating circuits outputting a signal which has delayed the falling edge of said input signal and a signal which has delayed the rising edge of said input signal, respectively.